Arithmetic with the Two-Dimensional Logarithmic Number System PDF
Preview Arithmetic with the Two-Dimensional Logarithmic Number System
UUnniivveerrssiittyy ooff WWiinnddssoorr SScchhoollaarrsshhiipp aatt UUWWiinnddssoorr Electronic Theses and Dissertations Theses, Dissertations, and Major Papers 2011 AArriitthhmmeettiicc wwiitthh tthhee TTwwoo--DDiimmeennssiioonnaall LLooggaarriitthhmmiicc NNuummbbeerr SSyysstteemm ((22DDLLNNSS)) Mahzad Azarmehr University of Windsor Follow this and additional works at: https://scholar.uwindsor.ca/etd RReeccoommmmeennddeedd CCiittaattiioonn Azarmehr, Mahzad, "Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS)" (2011). Electronic Theses and Dissertations. 430. https://scholar.uwindsor.ca/etd/430 This online database contains the full-text of PhD dissertations and Masters’ theses of University of Windsor students from 1954 forward. These documents are made available for personal study and research purposes only, in accordance with the Canadian Copyright Act and the Creative Commons license—CC BY-NC-ND (Attribution, Non-Commercial, No Derivative Works). Under this license, works must always be attributed to the copyright holder (original author), cannot be used for any commercial purposes, and may not be altered. Any other use would require the permission of the copyright holder. Students may inquire about withdrawing their dissertation and/or thesis from this database. For additional inquiries, please contact the repository administrator via email ([email protected]) or by telephone at 519-253-3000ext. 3208. Arithmetic with the Two-Dimensional Logarithmic Number System (2DLNS) by Mahzad Azarmehr A Dissertation Submitted to the Faculty of Graduate Studies through the Department of Electrical and Computer Engineering in Partial Ful(cid:2)llment of the Requirements for the Degree of Doctor of Philosophy at the University of Windsor Windsor,Ontario,Canada 2011 c 2011MahzadAzarmehr (cid:13) All Rights Reserved. No Part of this document may be reproduced, stored or otherwise retained in a retreival system or transmitted in any form, on any medium by any means withoutpriorwrittenpermissionoftheauthor. ArithmeticwiththeTwo-DimensionalLogarithmicNumberSystem(2DLNS) by MahzadAzarmehr APPROVEDBY: D.Al-Khalili DepartmentofElectricalandComputerEngineering, RoyalMilitaryCollege A.Edrisy DepartmentofMechanical, AutomotiveandMaterialsEngineering, UniversityofWindsor R.Muscedere DepartmentofElectricalandComputerEngineering,University ofWindsor M.Khalid DepartmentofElectricalandComputerEngineering,University ofWindsor M.Ahmadi DepartmentofElectricalandComputerEngineering,University ofWindsor A.T.Alpas DepartmentofMechanical, AutomotiveandMaterialsEngineering, UniversityofWindsor September23,2011 Declaration of Previous Publication This thesis includes 2 original papers that have been previously published/submitted for publicationinpeerreviewedjournals,asfollows: ThesisChapter Publicationtitle Publicationstatus Chapters4and5 High-SpeedandLow-PowerRecon(cid:2)gurableArchitectureof2-digit2DLNS-basedRecursiveMultipliers Published Chapter6 Low-PowerFiniteImpulseResponse(FIR)FilterDesignusingTwo-DimensionLogarithmicNumberSystem(2DLNS)Representations Submitted IcertifythatIhaveobtainedawrittenpermissionfromthecopyrightowner(s)toinclude the above published material(s) in my thesis. I certify that the above material describes work completedduringmyregistrationas graduate studentat the Universityof Windsor. I declarethat,tothebestofmyknowledge,mythesisdoesnotinfringeuponanyone’scopy- right nor violate any proprietary rights and that any ideas, techniques, quotations, or any othermaterialfromtheworkofotherpeopleincludedinmythesis,publishedorotherwise, are fully acknowledged in accordance with the standard referencing practices. Further- more, to the extent that I have included copyrighted material that surpasses the bounds of fairdealingwithinthemeaningoftheCanadaCopyrightAct,IcertifythatIhaveobtained a written permissionfrom the copyrightowner(s) to include such material(s) in my thesis. I declare that this is a true copy of my thesis, including any (cid:2)nal revisions, as approved by my thesis committee and the Graduate Studies of(cid:2)ce, and that this thesis has not been iv DECLARATIONOFPREVIOUSPUBLICATION submittedforahigherdegreetoanyotherUniversityorInstitution. v Abstract The ever increasing demand for low power DSP applications has directed researchers to contemplate a variety of potential approaches in different contexts. Since DSP algorithms heavilyrelyonmultiplication,therearegrowingdemandsformoreef(cid:2)cientmultiplication structures. In this regard, using some alternative number systems, which inherently are capable of reducing the hardware complexity, have been studied. The Multi-Dimensional LogarithmicNumberSystem(MDLNS),amulti-digitandmulti-baseextensiontotheLog- arithmic Number System (LNS), is considered as an alternative to the traditional binary representation for selected applications. The MDLNS provides a reduction in the size of the number representation with a non-linear mapping and promises a lower cost realiza- tion of arithmetic operations with a reduced hardware complexity. In addition, using the recursive multiplication technique, which refers to the published multiplication algorithm that uses smaller multipliersto implementa larger operation, reduces the size of operands and corresponding partial additions. As part of this research, 2DLNS-based multiplica- tion architectures with two different levels of recursion are presented. These architectures combinesomeof the(cid:3)exibilityof software withthe highperformance of hardware by im- plementingthe recursive multiplicationschemes on a 2DLNS processing structure. These implementationsdemonstratethe ef(cid:2)ciency of 2DLNS in DSP applicationsand show out- vi ABSTRACT standing results in terms of operation delay and dynamic power consumption. We also demonstrate the application of recursive 2DLNS multipliers to recon(cid:2)gurable multiplica- tion architectures. These architectures are able to perform single and double precision multiplication, as well as fault tolerant and dual throughput single precision operations. Modern DSP processors, such as those used in hand-held devices, may (cid:2)nd considerable bene(cid:2)t from these high-performance, low-power, and high-speed recon(cid:2)gurable architec- tures. In the (cid:2)nal partof thisresearch work,recursive2DLNS multiplicationarchitectures have been applied to a FIR (cid:2)lter structure. These implementationsshow considerable im- provementtotheirbinarycounterpartsintermsofVLSI areaandpowerconsumption. vii Towhommademebelievethatwhere thereisawill,thereisaway. viii Acknowledgments Thereare severalpeoplewhodeservetobeacknowledgedfor theirgenerouscontributions to this project. I would (cid:2)rst like to express my sincere gratitude and appreciation to Dr. Majid Ahmadi, my supervisor, for his invaluable guidance throughout the course of this thesis work. I would also like to thank my committee members: Dr. Afsaneh Edrisy, Dr. Roberto Muscedere, Dr. Mohammed Khalid, and Dr. Dhamin Al-Khalili from the Royal MilitaryCollege for reviewing my thesisand their constructivecomments. Special thanks to Dr. Roberto Muscedere for his expert guidance and constant support throughout my study. I am deeply grateful to my friend and partner Hassan Haftbaradaran for his love and con- stant support and encouragement. I also sincerely appreciate my family and friends for theirsupport,helpandfriendship. ix
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