Zero To Mastery In Computer Architecture And Organisation- No.1 Computer Architecture And Organisation Book To Become Zero To Hero, This Book Covers A-Z ... Edition (Zero To Mastery Computer Series)

265 Pages·17.901 MB·English

by  Rajiv Jain, Vei Publishing, Ayaz Uddin (editor)

• Shadab Saifi (Illustrator) • Ayaz Uddin (Editor)
Vayu Education of India
2/25, Ansari Road, Darya Ganj, New Delhi-110 002
Copyright © Vayu Education of India
First Edition: 2022
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or
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DISCLAIMER
Errors, if any, are purely unintentional and readers are requested to communicate such errors to
the publisher to avoid discrepancies in future.
Published by:
AN ISO 9001:2008 CERTIFIED COMPANY
VAYU EDUCATION OF INDIA
2/25, ANSARI ROAD, DARYA GANJ, NEW DELHI-110 002
PH.: 011-41564440, MOB. [phone]
Contents
1.0 OBJECTIVES.................................................................................................................................. 3
1.1 INTRODUCTION ......................................................................................................................... 3
1.2 WHAT IS COMPUTER?............................................................................................................... 3
1.2.1 Concept of Digits, Byte & Word....................................................................................... 4
1.3 WHAT IS COMPUTER SOFTWARE?......................................................................................... 4
1.3.1 Opearting Systems............................................................................................................ 5
1.3.2 Hardware vs. System vs. Application............................................................................ 6
1.3.3 Services Provided by OS for Application Programs ..................................................... 6
1.3.4 Various Classification of OS............................................................................................ 6
1.4. MEMORY UNITS.......................................................................................................................... 7
1.4.1 Introduction ...................................................................................................................... 7
1.4.2 Basic Units of Measurement............................................................................................ 8
1.4.3 Memory Hierarchy........................................................................................................... 9
1.4.4 Cache Memory.................................................................................................................. 9
1.4.5 RAM, ROM, PROM, EPROM........................................................................................... 9
1.4.6 Primary Vs. Secondary Memory................................................................................... 10
1.4.7 Auxiliary Storage Devices-Magnetic Tape, Floppy Disk, Hard Disk, PAN-Drive... 10
1.4.8 Optical Disks: CD-R Drive, CD-RW disks, DVD, Blue ray Discs............................... 12
1.5 VON NEUMANN ARCHITECTURE....................................................................................... 13
1.6 FLYNN'S CLASSIFICATION OF COMPUTER........................................................................ 13
1.6.1 Single Instruction Single Data (SISD)........................................................................... 13
1.6.2 Multiple Instruction Single Data (MISD)..................................................................... 14
1.6.3 Multiple Instruction Multiple Data (MIMD)................................................................ 14
1.7 NUMBER SYSTEMS................................................................................................................... 14
1.7.1 Binary Number System.................................................................................................. 14
1.7.2 Octal Number System..................................................................................................... 16
1.7.3 Hexadecimal Number System....................................................................................... 17
1.7.4 Binary Arithmetic........................................................................................................... 19
1.7.5 BCD Addition ................................................................................................................. 23
1.7.6 Alphanumeric Code....................................................................................................... 23
1.8 REVIEW QUESTIONS................................................................................................................ 24
1.9 SUMMARY.................................................................................................................................. 25
1.10 CHECK YOUR PROGRESS 1 .................................................................................................... 25
2.0 OBJECTIVES................................................................................................................................ 26
vi Zero to Mastery in Computer Architecture and Organisation
2.1 INTRODUCTION.......................................................................................................................26
2.1 LOGIC GATES ............................................................................................................................ 27
2.1.1 Basic or Fundamentals Gates........................................................................................27
2.1.2 Universal Gate................................................................................................................29
2.1.3 Derived Gates..................................................................................................................30
2.1.4 Positive and Negative Logic..........................................................................................32
2.2 BOOLEAN ALGEBRA ............................................................................................................... 33
2.2.1 De Morgan's Theorems.................................................................................................. 36
2.3 GLOSSARY..................................................................................................................................38
2.4 ANSWERS TO CHECK YOUR PROGRESS QUESTIONS...................................................... 38
3.0 OBJECTIVES................................................................................................................................39
3.1 COMBINATIONAL LOGIC.......................................................................................................39
3.2 SEQUENTIAL LOGIC OR CIRCUIT......................................................................................... 39
3.3 TYPES OF COMBINATIONAL CIRCUIT.................................................................................41
3.3.1 Multiplexer or Data Selector.......................................................................................... 41
3.3.2 Demultiplexer .................................................................................................................42
3.3.3 Decoder............................................................................................................................43
3.3.4 En-coder........................................................................................................................... 45
3.3.5 Counters..........................................................................................................................46
3.4 TYPES OF SEQUENTIAL CIRCUIT.......................................................................................... 48
3.4.1 RS Flip Flop..................................................................................................................... 48
3.4.2 D flip flop......................................................................................................................... 50
3.4.3 JK Flip-flop ...................................................................................................................... 50
3.4.4 T Flip Flop ....................................................................................................................... 51
3.5 REGISTER....................................................................................................................................52
3.5.1 Data Register...................................................................................................................52
3.5.2 Shift Register................................................................................................................... 53
3.6 ADDER........................................................................................................................................57
3.6.1 Half Adder ...................................................................................................................... 58
3.6.2 Full Adder .......................................................................................................................59
3.7 GLOSSARY..................................................................................................................................60
3.8 REVIEW QUESTIONS................................................................................................................ 61
4.0 OBJECTIVE..................................................................................................................................62
4.1 BASICS OF COMPUTER ORGANIZATION & ARCHITECTURE........................................ 62
4.2 MICRO-ARCHITECTURE ......................................................................................................... 64
4.3 INPUT/OUTPUT........................................................................................................................64
4.4 HIGH-LEVEL PROGRAMMING LANGUAGE...................................................................... 65
4.4.1 High Level Language Vs Lower Level Language .......................................................65
4.5 CENTRAL PROCESSING UNIT...............................................................................................66
4.5.1 The Control Unit............................................................................................................. 66
4.6 MIPS/MFLOPS AND CPU PERFORMANCE......................................................................... 66
4.6.1 Using MIPS and MFLOPS as Performance Metrics .................................................... 68
4.7 ORGANIZATIONAL STRUCTURE ......................................................................................... 70
4.7.1 Pre-bureaucratic Structures...........................................................................................70
Contents vii
4.7.2 Bureaucratic Structures.................................................................................................. 70
4.7.3 Post-bureaucratic............................................................................................................ 71
4.7.4 Functional Structure....................................................................................................... 71
4.7.5 Divisional Structure ....................................................................................................... 71
4.7.6 Matrix Structure.............................................................................................................. 71
4.8 GLOSSARY.................................................................................................................................. 72
4.9 REVIEW QUESTIONS................................................................................................................ 73
5.0 OBJECTIVE.................................................................................................................................. 77
5.1 INTRODUCTION ....................................................................................................................... 77
5.2 WHAT IS ISA............................................................................................................................... 77
5.3 WHAT ARE THE ELEMENTS OF AN INSTRUCTION? ....................................................... 78
5.4 CLASSIFICATION OF INSTRUCTION SET ARCHITECTURE............................................. 80
5.4.1 Complex Instruction Set Computer (CISC)................................................................... 80
5.4.2 Risc(Reduced Instruction Set Computer)..................................................................... 83
5.5 CISC/RISC DESIGN ISSUES..................................................................................................... 85
5.6 RISC VERSUS CISC .................................................................................................................... 85
5.7 COMPARISON OF RISC AND CISC ........................................................................................ 86
5.8 INTRODUCTION TO SOME OTHER IMPORTANT INSTRUCTION SET
ARCHITEC TURES..................................................................................................................... 90
5.9 GLOSSARY.................................................................................................................................. 92
5.10 REVIEW QUESTIONS................................................................................................................ 92
6.0 OBJECTIVES................................................................................................................................ 93
6.1 ADDRESSING MODES.............................................................................................................. 93
6.1.1 Immediate Addressing................................................................................................... 94
6.1.2 Direct or Absolute Addressing...................................................................................... 94
6.1.3 Implied Addressing........................................................................................................ 95
6.1.4 Relative Addressing....................................................................................................... 95
6.1.5 Indirect Addressing........................................................................................................ 95
6.1.6 Indexed Addressing....................................................................................................... 96
6.2 INSTRUCTIONS......................................................................................................................... 99
6.2.1 Data Transfer Instructions............................................................................................. 99
6.2.2 Data Manipulation Instructions/Data Processing Instructions.............................100
6.2.3 Program Control Instructions .....................................................................................102
6.3 MISCELLANEOUS/PRIVILEGE ............................................................................................103
6.4 INSTRUCTION SET AND FORMAT DESIGN ISSUES ........................................................105
6.5 INSTRUCTION SET: OPERATIONS ......................................................................................106
6.6 MAJOR SYSTEMS ACQUISITION MANUAL (MSAM) .......................................................106
6.6.1 Major Systems Acquisition Management ..................................................................106
6.6.2 Major Systems Acquisition Process Structure ...........................................................107
6.7 MODELING AND SIMULATION...........................................................................................108
6.7.1 Msam Using Simulation..............................................................................................108
6.8 GLOSSARY................................................................................................................................108
6.9 REVIEW QUESTIONS..............................................................................................................109
viii Zero to Mastery in Computer Architecture and Organisation
7.0 OBJECTIVE................................................................................................................................113
7.1 INTRODUCTION .....................................................................................................................113
7.2 CPU ARCHITECTURE.............................................................................................................113
7.3 ORGANIZATION OF CPU......................................................................................................117
7.3.1 Register Set....................................................................................................................117
7.3.2 Arithmetic Unit.............................................................................................................122
7.3.3 Control Unit ..................................................................................................................123
7.4 CPU DATAPATH.....................................................................................................................131
7.4.1 One-bus Organization .................................................................................................132
7.4.2 Two Bus Organization.................................................................................................133
7.4.3 Three-Bus Organization ..............................................................................................133
7.4.4 Single Cycle Datapath Vs Multicycle Datapath........................................................134
7.5 GLOSSARY................................................................................................................................134
7.6 REVIEW QUESTIONS..............................................................................................................135
8.0 OBJECTIVES..............................................................................................................................137
8.1 ADDRESSING MODES............................................................................................................137
8.1.1 Immediate Mode...........................................................................................................139
8.1.2 Direct (Absolute) Mode................................................................................................139
8.1.3 Indirect Mode................................................................................................................140
8.1.4 Indexed Mode ...............................................................................................................141
8.1.5 Other Modes..................................................................................................................141
8.2 INSTRUCTION FORMATS......................................................................................................143
8.3 INSTRUCTION CYCLE(FETCH – EXECUTE- DECODE-RELOAD CYCLE).....................144
8.3.1 Instruction cycle in Other Architectures of CPU.......................................................147
8.4 GLOSSARY................................................................................................................................148
8.5 REVIEW QUESTIONS..............................................................................................................149
9.0 OBJECTIVES..............................................................................................................................150
9.1 EXTERNAL DEVICES..............................................................................................................150
9.2 INPUT VS OUTPUT MODULE...............................................................................................151
9.3 MODES OF TRANSFERS.........................................................................................................152
9.3.1 Programmed I/O..........................................................................................................152
9.3.2 Interrupt Driven I/O ....................................................................................................152
9.3.3 Direct Memory Access..................................................................................................156
9.4 MEMORY HIERARCHY AND ITS NEED MEMORY ..........................................................159
9.5 THE MEMORY HIERARCHY.................................................................................................159
9.6 MAIN MEMORY.......................................................................................................................162
9.7 CACHE MEMORY....................................................................................................................167
9.7.1 Principle of Locality.....................................................................................................169
9.7.2 Cache Operation – overview.......................................................................................169
9.7.3 Cache Performance.......................................................................................................170
9.7.4 Cache Memory Organization......................................................................................171
9.7.5 Cache Write...................................................................................................................174
Contents ix
9.8 SECONDRY MEMORY............................................................................................................174
9.9 GLOSSARY................................................................................................................................177
9.10 REVIEW QUESTIONS..............................................................................................................178
10.0 OBJECTIVES..............................................................................................................................181
10.1 INTRODUCTION TO PARALLELISM...................................................................................181
10.1.1 Goals of Parallelism.....................................................................................................182
10.1.2 Uses of Parallelism.......................................................................................................182
10.1.3 Why Use Parallel Computing .....................................................................................183
10.1.4 Techniques of Concurrency.........................................................................................184
10.2 AMDAHL’S LAW.....................................................................................................................184
10.3 INSTRUCTION-LEVEL PARALLELISM (ILP) ......................................................................186
10.4 PROCESSOR-LEVEL PARALLELISM (PLP) .........................................................................188
10.5 PARALLEL COMPUTER MEMORY ARCHITECTURES.....................................................189
10.5.1 Shared Memory.............................................................................................................189
10.5.2 Distributed Memory.....................................................................................................191
10.5.3 Hybrid Distributed-Shared Memory ..........................................................................192
10.6 DESIGN LIMITATION OF PARALLEL APPLICATIONS....................................................193
10.7 GLOSSARY................................................................................................................................195
10.8 REVIEW QUESTIONS..............................................................................................................196
11.0 OBJECTIVE................................................................................................................................198
11.1 INTRODUCTION .....................................................................................................................198
11.2 VARIOUS CATEGORIES OF INSTRUCTION.......................................................................199
11.3 TIMING CONTROL..................................................................................................................203
11.3.1 Bus Request and Bus Grant Timings in Minimum Mode
System of 8086 ..............................................................................................................205
11.3.2 Memory Write Timing in Maximum mode of 8086...................................................206
11.3.3 RQ/GT Timings in Maximum Mode..........................................................................206
11.4 INSTRCTION FORMATS.........................................................................................................207
11.4.1 General Instruction Format .........................................................................................207
11.4.2 Three Instruction Formats ...........................................................................................209
11.5 GLOSSARY................................................................................................................................213
11.6 REVIEW QUESTIONS..............................................................................................................214
12.0 OBJECTIVES..............................................................................................................................215
12.1 INTRODUCTION .....................................................................................................................215
12.2 INTERRUPT TYPES.................................................................................................................216
12.2.1 Maskable Interrupt(MI)................................................................................................217
12.2.2 Non-maskable Interrupt ..............................................................................................217
12.2.3 Inter-Processor Interrupt..............................................................................................217
12.2.4 Software Interrupt.........................................................................................................217
12.2.5 Spurious Interrupt........................................................................................................217
12.3 TYPES OF INTERRUPTS.........................................................................................................217
x Zero to Mastery in Computer Architecture and Organisation
12.3.1 Level-triggered..............................................................................................................217
12.3.2 Edge-triggered...............................................................................................................217
12.3.3 Hybrid Interrupt...........................................................................................................218
12.3.4 Message-signaled Interrupt.........................................................................................218
12.3.5 Doorbell.........................................................................................................................219
12.4 ITERURRUPT IN 8086.............................................................................................................219
12.4.1 Advantages of Interrupts.............................................................................................219
12.4.2 Interrupt Latency..........................................................................................................220
12.4.3 Interrupt Response Time..............................................................................................220
12.5 STACK ORGANIZATION.......................................................................................................220
12.5.1 Register Stack................................................................................................................221
12.5.2 Memory Stack................................................................................................................222
12.5.3 Reverse Polish Notation ..............................................................................................223
12.6 GLOSSARY................................................................................................................................224
12.7 REVIEW QUESTIONS..............................................................................................................225
13.0 OBJECTIVES..............................................................................................................................226
13.1 INTRODUCTION .....................................................................................................................227
13.2 PROBLEMS WITH THE MEMORY SYSTEM........................................................................227
13.3 CACHE MEMORY....................................................................................................................229
13.4 CACHE ORGANIZATION......................................................................................................231
13.4.1 Direct Mapping.............................................................................................................231
13.4.2 Two-way Set-associative Cache..................................................................................233
13.4.3 Associtative Mapping..................................................................................................234
13.5 REPLACEMENT ALGORITHMS............................................................................................235
13.6 WRITE STRATEGIES ...............................................................................................................236
13.6.1 Write-through ...............................................................................................................236
13.6.2 Write-through with Buffered Write.............................................................................236
13.6.3 Copy-back......................................................................................................................236
13.7 WHAT IS VIRTUAL MEMORY...............................................................................................237
13.7.1 Virtual Memory Organization - Demand Paging......................................................238
13.8 ADDRESS TRANSLATION.....................................................................................................239
13.9 PAGE TABLE............................................................................................................................239
13.10 PAGE REPLACEMENT...........................................................................................................241
13.11 CONTROL MEMORY& MICRO-PROGRAM SEQUENCER:..............................................241
13.11.1 Why Control Memory...................................................................................................243
13.12 DEFINING A MICROINSTRUCTION FORMAT...................................................................244
13.13 WHAT IS MICRO-OPERATION.............................................................................................244
13.14 WHAT IS ADDREES SEQUENCING? ...................................................................................245
13.15 WHAT ARE COMPUTER REGISTERS..................................................................................245
13.15.1 Register Transfer Language (RTL)..............................................................................246
13.16 GLOSSARY................................................................................................................................246
13.17 REVIEW QUESTIONS..............................................................................................................247