Wireless Radio-Frequency Standards and System Design - Advanced Techniques

358 Pages·2012·16.354 MB·English

by  Cornetta, Gianluca, Santos, David J., Vázquez, José Manuel

Wireless Radio-Frequency
Standards and System
Design:
Advanced Techniques
Gianluca Cornetta
Universidad San Pablo-CEU, Spain & Vrije Universiteit Brussel, Belgium
David J. Santos
Universidad San Pablo-CEU, Spain
José Manuel Vázquez
Universidad San Pablo-CEU, Spain
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Library of Congress Cataloging-in-Publication Data
Wireless radio-frequency standards and system design : advanced techniques / Gianluca Cornetta, David J. Santos, and Jose
Manuel Vazquez, editors.
p. cm.
Includes bibliographical references and index.
ISBN 978-1-4666-0083-6 (hardcover) -- ISBN 978-1-4666-0084-3 (ebook) -- ISBN 978-1-4666-0085-0 (print & perpetual
access) 1. Radio frequency integrated circuits--Design and construction. 2. Systems on a chip. 3. Metal oxide semiconduc-
tors, Complementary. I. Cornetta, Gianluca, 1969- II. Santos, David J., 1967- III. Vazquez, Jose Manuel, 1954-
TK7874.78.W57 2012
621.384’12--dc23
2011048062
British Cataloguing in Publication Data
A Cataloguing in Publication record for this book is available from the British Library.
All work contributed to this book is new, previously-unpublished material. The views expressed in this book are those of the
authors, but not necessarily of the publisher.
xi
Preface
The amazing progress experienced by CMOS VLSI technology in the last decade, in the pursuit of an
ever increasing scaling of the feature size, has led to extremely tiny devices. The scaling of transistor
size has improved not only the achievable level of integration, but also the transistor switching speed.
This, in turn, has disclosed new potential applications for CMOS technology in high-performance RF
communication systems and devices.
In state-of-the-art CMOS processes it is quite common to have transistors with a unity current gain
frequency (f ) larger than 100 GHz, which makes these devices suitable for very high-frequency ap-
T
plications that were once dominated by bipolar, BiCMOS, and GaAs technologies. Fully-CMOS radio
transceivers and systems-on-chip are rapidly gaining popularity and increasing their share into the
wireless market. Moreover, RF CMOS technologies bring with them new architectures and astonish-
ing levels of integration that cannot be achieved with other technologies. CMOS technology brought
with it new transceiver topologies and circuit techniques. The traditional super-heterodyne receiver
was soon replaced by homodyne architectures with direct conversion to baseband, much more suitable
for a fully monolithic implementation in CMOS. On the other hand, monolithic planar inductors with
decent quality factors were soon available, allowing the design of tunable amplifiers, on-chip matching
networks, source-degenerated amplifiers, et cetera. Consequently, RF CMOS technology has become
the dominant technology for applications such as GPS receivers, GSM cellular transceivers, wireless
LAN, and wireless short-range personal area networks based on IEEE 802.15.1 (Bluetooth) or IEEE
802.15.4 (ZigBee) standards. In many cases, such transceivers must meet very aggressive design goals
such as low cost, low-power dissipation, and light weight. CMOS integrated circuits for RF applications
are being intensely studied due to their potential for low cost, high scalability, and integration, which
makes them suitable for Systems on Chip (SoC) implementations.
Mastering good design practices in the CMOS RF area has become a necessity for current RF Engi-
neers. Traditional design practices are now undergoing a process of deep changes that will leave behind
the now mature analog-based techniques, and will gradually move into software-controlled, mainly
digital architectures (the so-called, Software Defined Radio paradigm). In addition, the introduction of
deep-submicron processes (90 nm and below) poses new severe design problems and challenges.
This book introduces the RF designer to this brave new world. The RF designer in mind is a graduate
or PhD student in the RF area, or a practicing professional who needs a better insight on radio frequency
circuit and systems design. In both cases, the objective is to present in a single volume most of the hot-
test topics and latest developments in the RF area.
The book is divided into three sections:
xii
1. Novel techniques, Design and Simulation
2. RF-MEMS and Passive Devices
3. Baseband Processing and Wireless Standards
Section 1 (Chapters 1 to 5) explores new design practices, simulation techniques, and applications.
It comprises five chapters dealing with topics such as LNA linearization, low power design based on
the g /I technique, and behavioral modeling and co-simulation of analog and mixed-signal complex
m D
blocks for RF applications.
Section 2 (Chapters 6 to 8) deals with integrated passive devices for RF-ICs; both standard planar
monolithic devices (capacitor and inductors) and MEMS (Micro-electromechanical Systems) are thor-
oughly treated. SAW (Surface Acoustic Waves) and BAW (Bulk Acoustic Waves) design and imple-
mentation issues are presented and analyzed, as well as all the issues related with their integration with
bulk CMOS processes.
Finally, Section 3 (Chapters 9 to 12) covers baseband design techniques and wireless standards. Also,
hardware techniques for the implementation of multi-mode multi-standard, OFDM, and MIMO transceiv-
ers, as well as emerging standards like mobile WiMax, are presented and comprehensively discussed.
Enjoy the reading!
Gianluca Cornetta
Universidad San Pablo-CEU, Spain & Vrije Universiteit Brussel, Belgium
David J. Santos
Universidad San Pablo-CEU, Spain
José Manuel Vázquez
Universidad San Pablo-CEU, Spain
July 2011
Detailed Table of Contents
Preface ...................................................................................................................................................xi
Acknowledgment ................................................................................................................................xiii
Section 1
Novel Techniques, Design and Simulation
Chapter 1
Optimization of Linearity in CMOS Low Noise Amplifier ....................................................................1
Thierry Taris, University Bordeaux I, France
Aya Mabrouki, University Bordeaux I, France
In this chapter the authors evaluate a new and promising solution to the problem of power consump-
tion based on “optimum gate biasing.” This technique consists in tracking the MOS operating region
wherein the third derivation of drain current is zero. The method leads to a significant IIP3 improvement;
however, the sensitivity to process drifts requires the use of a specific bias circuit to track the optimum
biasing condition.
Chapter 2
An All-Inversion-Region g /I Based Design Methodology for Radiofrequency Blocks in CMOS
m D
Nanometer Technologies .......................................................................................................................15
Rafaella Fiorelli, University of Seville, Spain & Instituto de Microelectrónica de Sevilla, Spain
Eduardo Peralías, Instituto de Microelectrónica de Sevilla, Spain
Fernando Silveira, Universidad de la República, Uruguay
This chapter presents a design optimization methodology for analog radiofrequency (RF) blocks based
on the gm/ID technique and on the exploration of all-inversion regions (from weak inversion or sub-
threshold to strong inversion or above threshold) of the MOS transistor in nanometer technologies. The
use of semi-empirical models of MOS transistors and passive components, as inductors or capacitors,
assure accurate designs, reducing time and efforts for transferring the initial block specifications to a
compliant design. This methodology permits the generation of graphical maps to visualize the evolution
of the circuit characteristics when sweeping both the inversion zone and the bias current, allowing reach-
ing very good compromises between performance aspects of the circuit (e.g. noise and power consump-
tion) for a set of initial specifications. In order to demonstrate the effectiveness of this methodology, it is
applied in the design of two basic blocks of RF transceivers: low noise amplifiers (LNAs) and voltage
controlled oscillators (VCOs), implemented in two different nanometer technologies and specified to
be part of a 2.4 GHz transceiver. A possible design flow of each block is provided; resulting designs are
implemented and verified both with simulations and measurements.
Chapter 3
Wireless Interface at 5.7 GHz for Intra-Vehicle Communications: Sensing, Control and Multimedia ........40
J. P. Carmo, University of Minho, Portugal
J. H. Correia, University of Minho, Portugal
This chapter presents a wireless interface for intra vehicle communications (data acquisition from sensors,
control and multimedia) at 5.7 GHz. As part of the wireless interface, a RF transceiver was fabricated in
the UMC 0.18 μm RF CMOS process and when activated, it presents a total power consumption is 23
mW with the voltage supply of 1.5 V. This allows the use of only a coin sized battery for supplying the
interface. The carrier frequency can be digitally selectable and take one of 16 possible frequencies in the
range 5.42 5.83 GHz, adjusted in steps of 27.12 MHz. These multiple carriers allow a better spectrum
allocation and at the same time will improve the channel capacity due to the possibility to allow multiple
accesses with multiple frequencies.
Chapter 4
Simulation Techniques for Improving Fabrication Yield of RF-CMOS ICs ........................................61
Amparo Herrera, University of Cantabria, Spain
One of the industry sectors with the largest revenue in the telecommunication field is the wireless com-
munications field. Wireless operators compete for being the first to place their products in the market to
obtain the highest revenues. Moreover, they try to offer products that fulfill the user demands in terms
of price, battery life, and product quality. All these requirements must be also fulfilled by the designer
of the MMIC (Microwave Monolithic Integrated Circuits) circuits that will be used in those wireless
terminals, achieving a reliable design with high performance, low cost, and if possible, in one or two
foundry iterations, to bring the product out to the market as soon as possible.
Chapter 5
Σ-Δ Fractional-N Phase-Locked Loop Design Using HDL and Transistor-Level Models for Wireless
Communications ...................................................................................................................................99
Ahmed El Oualkadi, Abdelmalek Essaadi University, Morocco
This chapter presents a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on hard-
ware description language behavioral modeling. The proposed design consists of describing the mixed
behavior of this PLL architecture starting from the specifications of each building block. The descrip-
tion language models of critical PLL blocks have been described in VHDL-AMS, which is an IEEE
standard, to predict the different specifications of the PLL. The effect of different noise sources has been
efficiently introduced to study the overall system performances. The obtained results are compared with
transistor-level simulations to validate the effectiveness of the proposed models in the frequency range
around 2.45 GHz for wireless applications.
Section 2
RF-MEMS and Passive Devices
Chapter 6
RF-MEMS Based Oscillators .............................................................................................................120
Anis Nurashikin Nordin, International Islamic University Malaysia, Malaysia
Today’s high-tech consumer market demands complex, portable personal wireless consumer devices
that are low-cost and have small sizes. Creative methods of combining mature integrated circuit (IC)
fabrication techniques with innovative radio-frequency micro-electro-mechanical systems (RF-MEMS)
devices have given birth to wireless transceiver components operated at higher frequencies but manu-
factured at the low-cost of standard ICs. Oscillators, RF bandpass filters, and low noise amplifiers are
the most critical and important modules of any wireless transceiver. Their individual characteristics
determine the overall performance of a transceiver. This chapter illustrates RF-oscillators, which utilize
MEMS devices such as resonators, varactors, and inductors for frequency generation. Emphasis will
be given on state of the art RF-MEMS components such as film bulk acoustic wave, surface acoustic
wave, flexural mode resonators, lateral and vertical varactors, and solenoid and planar inductors. The
advantages and disadvantages of each device structure are described, with reference to the most recent
work published in the field.
Chapter 7
RF-MEMS Components for Wireless Transceivers ............................................................................156
Masoud Baghelani, Sahand University of Technology, Iran
Habib Badri Ghavifekr, Sahand University of Technology, Iran
Afshin Ebrahimi, Sahand University of Technology, Iran
The aim of this chapter is to provide the reader with deep information in the field of RF MEMS, covering
their current and possible applications, design, modeling, and simulation. Also, their problems, such as
power handling, packaging, frequency extension, etcetera, are discussed. In addition, this chapter will
introduce case studies in RF MEMS area for researchers.
Chapter 8
Passive Components for RF-ICs .........................................................................................................189
Gianluca Cornetta, Universidad San Pablo-CEU, Spain & Vrije Universiteit Brussel, Belgium
David J. Santos, Universidad San Pablo-CEU, Spain
José Manuel Vázquez, Universidad San Pablo-CEU, Spain
The modern wireless communication industry is demanding transceivers with a high integration level
operating in the gigahertz frequency range. This, in turn, has prompted an intense research in the area
of monolithic passive devices. Modern fabrication processes provide now the capability to integrate
onto a silicon substrate inductors and capacitors, enabling a broad range of new applications. Inductors
and capacitors are the core elements of many circuits, including low-noise amplifiers, power amplifiers,
baluns, mixers, and oscillators, as well as fully-integrated matching networks. While the behavior and
the modeling of integrated capacitors are well understood, the design of an integrated inductor is still
a challenging task since its magnetic behavior is hard to predict accurately. As the operating frequency
approaches the gigahertz range, device nonlinearities, coupling effects, and skin effect dominate, mak-
ing difficult the design of critical parameters such as the self-resonant frequency, the quality factor,
and self and mutual inductances. However, despite the parasitic effects and the low quality-factor, the
integrated inductors still allow the implementation of integrated circuits with improved performances
under low supply voltage. In this chapter, the authors review the technology behind monolithic capaci-
tors and inductors on silicon substrate for high-frequency applications, with major emphasis on physical
implementation and modeling.
Section 3
Baseband Processing and Wireless Standards
Chapter 9
Frequency Synchronization for OFDM/OFDMA Systems .................................................................216
Javier González Bayón, Universidad Politécnica de Madrid, Spain
Carlos Carreras Vaquer, Universidad Politécnica de Madrid, Spain
Angel Fernández Herrero, Universidad Politécnica de Madrid, Spain
Orthogonal frequency division multiplexing (OFDM) has been the focus of many studies in wireless
communications because of its high transmission capability and its robustness to the effects of frequency-
selective multipath channels. However, it is well known that OFDM systems are much more sensitive to a
carrier frequency offset (CFO) than single carrier schemes with the same bit rate. Therefore, a frequency
synchronization process is necessary to overcome this sensitivity to frequency offset. Synchronization
is performed in two stages: acquisition and tracking. After a first estimation and correction of the CFO
performed in the acquisition stage, there still remains a residual frequency offset (RFO) due to real system
conditions. Therefore, the RFO tracking has to be performed for all the receiving data.
Chapter 10
Design Issues for Multi-Mode Multi-Standard Transceivers ..............................................................237
Gianluca Cornetta, Universidad San Pablo-CEU, Spain & Vrije Universiteit Brussel, Belgium
David J. Santos, Universidad San Pablo-CEU, Spain
José Manuel Vázquez, Universidad San Pablo-CEU, Spain
Multi-mode and multi-band transceivers, i.e. transceivers with the capability to operate in different
frequency bands and to support different waveforms and signaling schemes, are objects of intense
study. In fact, hardware reuse among different standards would help to reduce production costs, power
consumption, and to increase the integration level of a given implementation. The design of such
transceivers is indeed very complex, because it not only implies the choice of the architecture more
suitable for the target application, but also the choice and the design of reconfigurable building blocks
to perform tuning among the different standards and signaling schemes. In addition, different standards
may have considerably different requirements in terms of receiver sensitivity, linearity, input dynamic
range, error vector magnitude (EVM), signal bandwidth, and data rate, which in turn make the design
of a multi-mode reconfigurable transceiver a very challenging task. In this chapter, the authors pres-
ent the most common techniques and architecture schemes used in modern wireless communication
systems supporting standards for cellular, wireless local area networks (WLAN), and wireless personal
area networks (WPAN), i.e. GSM, WCDMA, IEEE 802.11 (Wi-Fi), IEEE 802.15.1 (Bluetooth), IEEE
802.15.4 (Zigbee), and IEEE 802.15.3 (UWB). State-of-the-art techniques for multi-standard cellular,
WLAN, and WPAN transceivers are thoroughly analyzed and reviewed, with special emphasis on those
relying on bandpass sampling and multi-rate signal processing schemes.
Chapter 11
Design and Implementation of Hardware Modules for Baseband Processing in Radio Transceivers:
A Case Study .......................................................................................................................................266
Angel Fernández Herrero, Universidad Politécnica de Madrid, Spain
Gabriel Caffarena Fernández, Universidad San Pablo-CEU, Spain
Alberto Jiménez Pacheco, École Polytechnique Fédérale de Lausanne, Switzerland
Juan Antonio López Martín, Universidad Politécnica de Madrid, Spain
Carlos Carreras Vaquer, Universidad Politécnica de Madrid, Spain
Francisco Javier Casajús Quirós, Universidad Politécnica de Madrid, Spain
In this chapter, the main aspects of the design of baseband hardware modules are addressed. Special at-
tention is given to word-length optimization, implementation, and validation tasks. As a case study, the
design of an equalizer for a 4G MIMO receiver is addressed. The equalizer is part of a communication
system able to handle up to 32 users and provide transmission bit-rates up to 125 Mbps. The word-length
optimization process are explained first, as well as techniques to reduce computation times. Then, the
case study are presented and analyzed, and the different tasks and tools required for its implementation
are explained. FPGAs are selected as the target implementation technology due to its interest for the
DSP community.
Chapter 12
System Design Perspective: WiMAX Standards and IEEE 802.16j Based Multihop WiMAX .........287
Hrishikesh Venkataraman, Dublin City University (DCU), Ireland
Bogdan Ciubotaru, Dublin City University (DCU), Ireland
Gabriel-Miro Muntean, Dublin City University (DCU), Ireland
The next generation of cellular networks has evolved from voice-based to data-centric communication. The
recent focus has been mainly on high data-rate services like mobile gaming, high quality music, Internet
browsing, video streaming, etc. which consumes lots of bandwidth. This puts a severe constraint on the
available radio resource. In this chapter, the IEEE 802.16 based multihop WiMAX networks (802.16j)
is introduced, and the system design is explained in detail. The chapter outlines the background and the
importance of multihop wireless networks, especially in the cellular domain. Different types of multihop
design for WiMAX is explained, along with a detailed analysis of the effect of the number of hops in the
WiMAX networks. Further, in order to support next generation rich media services, the system design
requirements and challenges for real-time video transmission are explained.
Compilation of References ...............................................................................................................310
About the Contributors ....................................................................................................................335
Index ...................................................................................................................................................342
Section 1
Novel Techniques, Design and
Simulation