VLSI-SOC: From Systems to Chips: IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1–3, 2003, Darmstadt, Germany

315 Pages·2006·5.169 MB·English

by  Vijay Degalahal, R. Ramanarayanan (auth.), Manfred Glesner, Ricardo Reis, Leandro Indrusiak, Vincent Mooney, Hans Eveking (eds.)

VLSI-SOC: FROM SYSTEMS TO CHIPS
IFIP - The International Federation for Information Processing
IFIP was founded in 1960 under the auspices of UNESCO, following the First World
Computer Congress held in Paris the previous year. An umbrella organization for
societies working in information processing, IFIP's aim is two-fold: to support
information processing within its member countries and to encourage technology transfer
to developing nations. As its mission statement clearly states,
IFIP's mission is to be the leading, truly international, apolitical
organization which encourages and assists in the development,
exploitation and application of information technology for the benefit
of all people.
IFIP is a non-profitmaking organization, run almost solely by 2500 volunteers. It operates
through a number of technical committees, which organize events and publications.
IFIP's events range from an international congress to local seminars, but the most
important are:
• The IFIP World Computer Congress, held every second year;
• Open conferences;
• Working conferences.
The flagship event is the IFIP World Computer Congress, at which both invited and
contributed papers are presented. Contributed papers are rigorously refereed and the
rejection rate is high.
As with the Congress, participation in the open conferences is open to all and papers may
be invited or submitted. Again, submitted papers are stringently refereed.
The working conferences are structured differently. They are usually run by a working
group and attendance is small and by invitation only. Their purpose is to create an
atmosphere conducive to innovation and development. Refereeing is less rigorous and
papers are subjected to extensive group discussion.
Publications arising from IFIP events vary. The papers presented at the IFIP World
Computer Congress and at open conferences are published as conference proceedings,
while the results of the working conferences are often published as collections of selected
and edited papers.
Any national society whose primary activity is in information may apply to become a full
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members are entitled to vote at the annual General Assembly, National societies
preferring a less committed involvement may apply for associate or corresponding
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voting rights. Corresponding members are not represented in IFIP bodies. Affiliated
membership is open to non-national societies, and individual and honorary membership
schemes are also offered.
VLSI-SOC: FROM SYSTEMS
TO CHIPS
IFIP TC 10/ WG 10.5 Twelfth International Conference
on Very Large Scale Integration of System on Chip
(VLSI'SoC 2003), December 1-3, 2003, Darmstadt,
Germany
Edited by
Manfred Glesner
Technische Universitat, Darmstadt, DE
Ricardo Reis
UniversJdade Federal do Rio Grande do Sul, BR
Leandro Indrusiak
Technische Universitat, Darmstadt, DE
Vincent Mooney
Georgia Tech, LISA
Hans Eveking
Technische Universitat, Darmstadt, DE
Springer
Library of Congress Control Number: 2006923023
VLSI-SOC: From Systems to Chips
Edited by M. Glesner, R. Reis, L. Indrusiak, V. Mooney, and H. Eveking
p. cm. (IFIP International Federation for Information Processing, a Springer Series in
Computer Science)
ISSN: 1571-5736/ 1861-2288 (Internet)
ISBN: 10:0-387-33402-5
ISBN: 13: 9780-387-33402-5
elSBN: 10:0-387-33403-3
Printed on acid-free paper
Copyright © 2006 by International Federation for Information Processing.
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, Inc., 233 Spring Street, New York, NY
10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in
connection with any form of information storage and retrieval, electronic adaptation, computer software,
or by similar or dissimilar methodology now known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms, even if they are
not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject
to proprietary rights.
Printed in the United States of America.
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CONTENTS
Preface ix
Effect of Power Optimizations on Soft Error Rate 1
Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan,
Y. Xie, M. J. Irwin
Dynamic Models for Substrate Coupling in Mixed-Mode Systems 21
Jodo M. S. Silva, Luis Miguel Silveira
HINOC: A Hierarchical Generic Approach for On-Chip 39
Communication, Testing and Debugging of SoCs
Thomas Hollstein, RalfLudewig, Heiko Zimmer, Christoph Mager,
Simon Hohenstern, Manfred Glesner
Automated Conversion of SystemC Fixed-Point Data Types 55
Axel G. Braun, Djones V. Lettnin, Joachim Gerlach,
Wolfgang Rosenstiel
Exploration of Sequential Depth by Evolutionary Algorithms 73
Nicole Drechsler, RolfDrechsler
Validation of Asynchronous Circuit Specifications Using IF/CADP 85
Dominique Borrione, Menouer Boubekeur, Laurent Mounier,
Marc Renaudin, Antoine Siriani
On-Chip Property Verification Using Assertion Processors 101
Jose Augusto M, Nacif Claudionor Nunes Coelho Jr., Harry Foster,
Fldvio Miana de Paula, Edjard Mota, Mdrcia Roberta Falcdo Mota,
Antonio Otdvio Fernandes
VI
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized 119
Real-Time Systems
Jurgen Becker, Michael Hubner, Michael Ullmann
A Switched Opamp Based 10 Bits Integrated ADC for Ultra 133
Low Power Applications
Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti,
Cristian Garbossa, Luca Colombini, Maurizio Bacci,
Stefania Chicca, Franco Bigongiari
Exploring the Capabilities of Reconfigurable Hardware for 149
OFDM-based WLANs
Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
Software-Based Test for Non-Programmable Cores in 165
Bus-Based System-on-Chip Architectures
Alexandre M. Amory, Leandro A. Oliveira, Fernando G. Moraes
Optimizing SoC Test Resources Using Dual Sequences 181
Wei Zou, Chris C.N. Chu, Sudhakar M. Reddy, Irith Pomeranz
A Novel Full Automatic Layout Generation Strategy For 197
Static CMOS Circuits
Cristiano Lazzari, Cristiano Domingues, Jose GUntzel,
Ricardo Reis
Low Power Java Processor for Embedded Applications 213
Antonio Carlos S. Beck, Luigi Carro
Impact of Gate Leakage on Efficiency of Circuit Block 229
Switch-Off Schemes
Stephan Henzler, Philip Teichmann, Markus Koban,
Jorg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel
Evaluation Methodology for Single Electron Encoded 247
Threshold Logic Gates
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
Asynchronous Integration of Coarse-Grained Reconfigurable 263
XPP-Arrays into Pipelined RISC Processor Datapath
JUrgen Becker, Alexander Thomas, Maik Scheer
Contents vii
Gray Encoded Arithmetic Operators Applied to FFT 281
and FIR Dedicated Datapaths
Eduardo A. C. da Costa, Jose C Monteiro, Sergio Bampi
Stuck-at-FauIt Testability of SPP Three-Level Logic Forms 299
Valentina Ciriani, Anna Bernasconi, RolfDrechsler
PREFACE
This book contains extended and revised versions of the best
papers that have been presented during the twelfth edition of the IFIP
TC10/WG10.5 International Conference on Very Large Scale
Integration, a Global System-on-a-Chip Design & CAD Conference.
The 12* edition was held at the Lufthansa Training Center in
Seeheim-Jugenheim, south of Darmstadt, Germany (December 1-3,
2003). Previous conferences have taken place in Edinburgh (81),
Trondheim (83), Tokyo (85), Vancouver (87), Munich (89),
Edinburgh (91), Grenoble (93), Tokyo (95), Gramado (97), Lisbon
(99)andMontpellier(01).
The purpose of this conference, sponsored by IFIP TC 10 Working
Group 10.5, is to provide a forum to exchange ideas and show
research results in the field of microelectronics design. The current
trend toward increasing chip integration brings about exhilarating new
challenges both at the physical and system-design levels: this
conference aims to address these exciting new issues.
The 2003 edition of VLSI-SoC conserved the traditional structure,
which has been successful in previous editions. The quality of
submissions (142 papers) made the selection process difficult, but
finally 57 papers and 14 posters were accepted for presentation in
VLSI-SoC 2003. Submissions came from Austria, Bulgaria, Brazil,
Canada, Egypt, England, Estonia, Finland, France, Germany, Greece,
Hungary, India, Iran, Israel, Italy, Japan, Korea, Malaysia, Mexico,
Netherlands, Poland, Portugal, Romania, Spain, Sweden, Taiwan and
the United States of America. From 57 papers presented at the
conference, 18 were selected to have an extended and revised version
included in this book.
This book also includes the paper "Effect of Power Optimizations
on Soft Error Rate" which one is related to a tutorial presented by
Narayanan Vijaykrishnan, Penn State University,
VLSI-SoC 2003 was the work of many dedicated volunteers: paper
authors, reviewers, session chairs, invited speakers and chairs of
various aspects, especially the local arrangements by the various
members of the Institut fur Mikroelektronische Systeme of
Technische Universitat Darmstadt and the financial management by
the VDE Information Technology Society. The edition of this book
was done with the significant help of Ana Cristina Pinto and Jane
FoUmann from UFRGS at Porto Alegre. We thank them all for their
contribution.
The editors