VLSI Design for Manufacturing: Yield Enhancement

298 Pages·1990·9.19 MB·English

by  Stephen W. Director

VLSI DESIGN FOR MANUFACTURING:
YIELD ENHANCEMENT
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
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Introduction to VLSI Silicon Devices: Physics, Technology and Characterization. B. EI-Kareh and
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Latchup in CMOS Technology: The Problem and Its Cure. R.R. Troutman. ISBN 0-89838-215-7.
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The Bounding Approach to VLSI Circuit Simulation. C.A. Zukowski. ISBN 0-89838-176-2.
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VLSI DESIGN FOR MANUFACTURING:
YIELD ENHANCEMENT
by
Stephen W. Director
Wojciech Maly
Andrzej J. Strojwas
Carnegie Mellon University
l1li...
"
KLUWER ACADEMIC PUBLISHERS
Boston/Dordrecht/London
Distributors for North America:
K1uwer Academic Publishers
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Assinippi Park
Norwell, Massachusetts 02061 USA
Distributors for all other countries:
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Distribution Centre
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Library of Congress Cataloging-in-Publication Data
Director, Stephen W.
VLSI design for manufacturing : yield enhancement / by Stephen W.
Director, Wojcilech Maly, Andrzej 1. Strojwas.
p. cm. - (Kluwer international series in engineering and
computer science. VLSI, computer architecture, and digital signal
processing)
Includes bibliographical references.
ISBN-13: 978-1-4612-8816-9 e-lSBN-13: 978-1-4613-1521-6
DOl: 10.1007/978-1-4613-1521-6
I. Integrated circuits-Very large scale integration-Design and
construction-Data processing. 2. Computer-aided design. I. Maly.
W. II. Strojwas. Andrzej J. III. Title. IV. Series.
TK7874.D555 1990
621.39 '5-dc20 89-37029
CIP
Copyright © 1990 by Kiuwer Academic Publishers
Softcover reprint of the hardcover 1st edition 1990
All rights reserved. No part of this publication may be reproduced. stored in a retrieval system or
transmitted in any form or by any means, mechanical, photocopying. recording. or otherwise.
without the prior written permission of the publisher, Kluwer Academic Publishers. 101 Philip
Drive, Assinippi Park, Norwell. Massachusetts 02061.
To our students
Table of Contents
1. Yield Estimation and Prediction 1
1.1. Introduction 1
1.2. The VLSI Fabrication Process 2
1.3. Disturbances in the IC Manufacturing Process 11
1.3.1. Process Disturbances 11
1.3.2. Process Related Deformations of IC Design 13
1.3.2.1. Geometrical Deformations 13
1.3.2.2. Electrical Deformations 18
1.3.3. General Characteristics of Process Disturbances 20
1.3.4. IC Performance Faults 20
1.4. Measures of Process Efficiency 22
1.4.1. Yield Estimation 23
1.4.2. Yield Prediction 26
1.4.3. Decomposition of the Design Yield Equations 29
1.5. Discussion 31
1.5.1. Relationships Between Manufacturing and Design Yields 31
1.5.2. Examples of Yield Analysis 33
1.5.3. Yield and Production Cost 37
1.6. Overview of the Sequel 40
2. Parametric Yield Maximization 43
2.1. Introduction 43
2.1.1. Definitions of Yield and Design Center 44
2.1.2. Design Centering By Simplicial Approximation 46
2.1.3. Design Centering Procedure 51
2.1.4. Scaling: Inscribing a Hyperellipsoid 55
2.1.5. Illustration of the Basic Method 58
2.2. Design Centering and Worst Case Design with Arbitrary 62
Statistical Distributions
2.2.1. Norm Bodies and PDF Norms 62
2.2.2. Generalized Simplicial Approximation 67
2.2.3. Mixed Worst-Case Yield Maximization 70
2.2.4. Tolerance Assignment 76
2.3. Example of Worst Case Design 79
2.4. A Dimension Reduction Procedure 81
viii TABLE OF CONTENTS
2.4.1. Design Centering in a Reduced Space 83
2.4.2. Discussion 85
2.5. Fabrication Based Statistical Design of Monolithic IC's 86
2.5.1. Independently Designable Parameters in Yield 87
Maximization of Monolithic IC's
2.5.2. Process Simulation and Yield Maximization 89
3. Statistical Process Simulation 93
3.1. Introduction 93
3.2. Statistical Process Simulation 94
3.2.1. Methodology 94
3.2.2. Modeling of Process Disturbances 97
3.2.3. Process and Device Models for Statistical Simulation 105
3.2.4. Models of Ion Implantation 106
3.2.5. MOS Transistor Model 108
3.2.6. Structure of the Simulator 109
3.3. Tuning of Process Simulator with PROMETHEUS 112
3.3.1. Mathematical Formulation 112
3.3.2. Methodology of Solution 115
3.4. The Process Engineer's Workbench 116
3.4.1. Process and Device Simulation 117
3.4.2. User Interaction-Process Synthesis 119
3.4.3. Internal Data Structures 121
3.4.4. User Interaction - Compiled Simulation 124
3.4.5. Extensions 128
4. Statistical Analysis 129
4.1. Statistical Timing Simulation 129
4.1.1. Overview 130
4.1.2. Our Approach 131
4.1.2.1. Timing reevaluation 136
4.1.3. Characterization 137
4.1.4. Delay decomposition 140
4.1.5. Nominal Simulation 143
4.1.6. Statistical Simulation 147
4.2. An Improved Worst-Case Analysis Procedure 152
4.2.1. Worst-Case Analysis Methodology 153
4.2.1.1. Algorithm for Worst-Case Analysis 156
4.2.2. A Software Package for Worst-Case Analysis 156
ix
4.2.3. Examples 158
4.3. Optimal Device and Cell Design Using FABRICS 166
4.3.1. Proposed Methodology 167
4.3.2. Description of Experiment 168
4.3.3. Building the Regression Model 171
4.3.4. Performance Optimization 172
5. Functional Yield 175
5.1. Introduction 175
5.2. Basic Characteristics of Spot Defects 176
5.2.1. Defect Mechanisms 177
5.2.2. Defect Spatial Distribution 177
5.2.3. Distribution of Defect Radii 184
5.2.4. Distribution of Defect Radii Within Layer 186
5.3. Yield Modeling Using Virtual Layout 189
5.3.1. Critical Area 190
5.3.2. Spot Defect Related Yield Losses 191
5.3.3. Yield Losses Due to Lateral Process Deformations 195
5.3.4. Critical Area Computation Using Virtual Layout 198
5.3.5. Examples of Application of the Virtual Layout Method 200
5.4. Monte Carlo Approach to Functional Yield Prediction 203
5.4.1. The \'LASIC Yield Simulator 204
5.4.2. Fault Analysis 205
5.4.3. \'LASIC Implementation and Summarizing Discussion 212
5.5. Yield Computations for \'LSI Cell 213
5.5.1. Probability of Failure (POF) for Simple Layout Patterns 213
5.5.2. POF for Macrocells 220
5.5.3. Implementation 228
6. Computer-Aided Manufacturing 229
6.1. Motivation 229
6.2. Overview of the CMU-CAM System 231
6.3. Statistical Process Control: The Unified Framework 233
6.3.1. Profit Function 236
6.4. CMU-CAM Software System 238
6.4.1. Decomposition 238
6.4.2. Modeling for Process Control 242
6.4.3. Statistical Quality Control 245
6.4.4. Acceptance and Rejection Criteria 249
x TABLE OF CONTENTS
6.4.5. Feed Forward Control 256
6.5. Computational Examples 260
6.5.1. Yield Enhancement 265
6.6. Conclusions 267
References 269
Index 285
Preface
One of the keys to success in the IC industry is getting a new product to
market in a timely fashion and being able to produce that product with
sufficient yield to be profitable. There are two ways to increase yield: by
improving the control of the manufacturing process and by designing the
process and the circuits in such a way as to minimize the effect of the
inherent variations of the process on performance. The latter is typically
referred to as "design for manufacture" or "statistical design". As device
sizes continue to shrink, the effects of the inherent fluctuations in the IC
fabrication process will have an even more obvious effect on circuit
performance. And design for manufacture will increase in importance. We
have been working in the area of statistically based computer aided design
for more than 13 years. During the last decade we have been working with
each other, and individually with our students, to develop methods and
CAD tools that can be used to improve yield during the design and
manufacturing phases of IC realization. This effort has resulted in a large
number of publications that have appeared in a variety of journals and
conference proceedings. Thus our motivation in writing this book is to put,
in one place, a description of our approach to IC yield enhancement. While
the work that is contained in this book has appeared in the open literature,
we have attempted to use a consistent notation throughout this book.
(Despite our best efforts thought there are times that inconsistency has crept
in and we ask the readers patience.) We have also decided to organize the
material by topic, rather than in chronological order. Thus it is not
necessarily true that the material presented in earlier chapters was actually
developed prior to the material presented in later chapters.
We begin in Chapter 1 by presenting a uniform framework of viewing yield
related problems in IC manufacture. The concepts of parametric and
functional yields are introduced and a number of important definitions and
assumptions are presented. Chapter 2 discusses the parametric yield
maximization problem and introduces the simplicial approximation method.
This method will also playa role in a computer aided manufacturing system