VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy

222 Pages·2007·3.923 MB·English

by  Liming Xiu

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VLSI Circuit Design
Methodology Demystified
A Conceptual Taxonomy
Liming Xiu
IEEE PRESS
WILEY-INTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
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VLSI Circuit Design
Methodology Demystified
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IEEE Press
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Piscataway, NJ 08854
IEEE Press Editorial Board
Mohamed E. El-Hawary, Editor in Chief
R. Abari T. Chen R. J. Herrick
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B. M. Hammerli
Kenneth Moore, Director of IEEE Book and Information Services (BIS)
Catherine Faduska, Senior Acquisitions Editor
Jeanne Audino,Project Editor
Technical Reviewers
Poras T. Balsara, University of Texas at Dallas
Peggy Ping Gui, Southern Methodist University
Gabriele Manganaro, National Semiconductor Corp.
Andrew Marshall, Texas Instruments, Inc.
ffirs.qxd 10/11/2007 9:07 AM Page iii
VLSI Circuit Design
Methodology Demystified
A Conceptual Taxonomy
Liming Xiu
IEEE PRESS
WILEY-INTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
ffirs.qxd 10/11/2007 9:07 AM Page iv
Copyright © 2008 by the Institute of Electrical and Electronics Engineers, Inc.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved.
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10 9 8 7 6 5 4 3 2 1
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To my wife, Zhihong,
my daughters, Katherine and Helen,
and my parents, Zunxin and Zhengfeng
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Contents
Foreword xi
Richard Templeton
Foreword xiii
Hans Stork
Preface xv
Acknowledgments xvii
CHAPTER 1 THE BIG PICTURE 1
1. What is a chip? 1
2. What are the requirements of a successful chip design? 3
3. What are the challenges in today’s very deep submicron 4
(VDSM), multimillion gate designs?
4. What major process technologies are used in today’s design 5
environment?
5. What are the goals of new chip design? 8
6. What are the major approaches of today’s very large scale 9
integration (VLSI) circuit design practices?
7. What is standard cell-based, application-specific integrated 11
circuit (ASIC) design methodology?
8. What is the system-on-chip (SoC) approach? 12
9. What are the driving forces behind the SoC trend? 15
10. What are the major tasks in developing a SoC chip from 15
concept to silicon?
11. What are the major costs of developing a chip? 16
CHAPTER 2 THE BASICS OF THE CMOS PROCESS 17
AND DEVICES
12. What are the major process steps in building MOSFET 17
transistors?
vii
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viii CONTENTS
13. What are the two types of MOSFET transistors? 19
14. What are base layers and metal layers? 20
15. What are wafers and dies? 24
16. What is semiconductor lithography? 28
17. What is a package? 33
CHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41
18. What is the role of functional verification in the IC 41
design process?
19. What are some of the design integrity issues? 44
20. What is design for testability? 46
21. Why is reducing the chip’s power consumption so important? 48
22. What are some of the challenges in chip packaging? 49
23. What are the advantages of design reuse? 50
24. What is hardware/software co-design? 51
25. Why is the clock so important? 54
26. What is the leakage current problem? 57
27. What is design for manufacturability? 60
28. What is chip reliability? 62
29. What is analog integration in the digital environment? 65
30. What is the role of EDA tools in IC design? 67
31. What is the role of the embedded processor in the SoC 69
environment?
CHAPTER 4 CELL-BASED ASIC DESIGN METHODOLOGY 73
32. What are the major tasks and personnel required in a chip 73
design project?
33. What are the major steps in ASIC chip construction? 74
34. What is the ASIC design flow? 75
35. What are the two major aspects of ASIC design flow? 77
36. What are the characteristics of good design flow? 80
37. What is the role of market research in an ASIC project? 81
38. What is the optimal solution of an ASIC project? 82
39. What is system-level study of a project? 84
40. What are the approaches for verifying design at the 85
system level?
41. What is register-transfer-level (RTL) system-level description? 86
42. What are methods of verifying design at the register-transfer- 87
level?
43. What is a test bench? 88
44. What is code coverage? 89