Verilog HDL Synthesis A Practical Primer

230 Pages·1999·5.12 MB·English

by  J. Bhasker

J. Bhasker :
VERILOG
HDL
SYNTHESIS

a
A Practical Primer
Veriloge HDL Synthesis
A Practical Primer
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Verilog: HDL Synthesis
A Practical Primer

Segeram
J BHASKER

Distinguished Member of Technical Staff
Bell Labs, Lucent Technologies

‘Star Galaxy Publishing
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BEL HE[eC

Copyright #1994 Lucene Texhnologios. All ights reserved

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Printed in the United States of America

10987654321

Library of Congress Catalog Card Number: 98-61058

ISBN 0.9650391-5.3
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Patten hat ele?

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{PSbeoe amen none Enos a")
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(a of gal ti eveyone goes eg I)
Koi sompha nahi, koi jana aubi
(Yo ne es ndesond une ee toate)

= A song from an Tian fl
Foreword

Preface

CHAPTER 1

Basics 1

Lt
12
ir
Ma,

CHarien2

‘Whe is Syathesis?, |
Spuulesis in a Design Prosest, 3
opie Value System, 6
Bic widths, 6
LAL, DatwIypes, 6
Nea Dite ype, 6
ester Dats Typ,
142, Conant, 9
143. Pananelers 10
‘Value Holder for Hardware Modeling, 10

Verilog Constructs to Gates 1s

2

‘Continuous Assignment Statement, 18
commer

22.

25,
26.
27.
22,
29.
210,

2b
212
Das.

214

245,

216.
an.

Procedural Assignment Statement, 17
22:1. Blocking Predoral Assigament, 17
22. Nomethcking Prvaral Assinneh, 18
22R Target Assignment, 19
BRC Asiemnen Restrictions, 20
Logical Operators, 21
Anuhmetic Operators, 22
2A. Ussigied Atchnete. 22
2A. Signed Arihmate, 23
BAS. Modeling a Cary 24
Relalivaal Opeatos, 25
Enpality Opetators, 27
Shit Operas, 28
Veetor Opeiations, 30
Pan-eelets, 32
Ritselets, 35
12101, ConmtnacLodes, 33
2.102, emevonsan Indes in Expression, 34
203, Semvonsan Iden ia Target, 35
Conditional Expression, 36
Always Statement, 27
Statement, 40
213.4. Tnfeing Lathes from If Sete, Al
Case Stalemienl, 45
2G, Case Strzment, 48
2142. Casex Statement. 4
2443. Infeaing Latches from Case Statements, 51
2444, Full. 52
DANS, Parallel Ci, 55
2.46, Non-consan 38 Cave Lem, 5
More on tnforting Latches, $9
Lat DecvedVasinble, 0
Varble Assigned fore Use, 61
Ga fore Assigned, 62
215.1._Larch wits Asyostwunous Preset and Cle, 64
Loop Stateren, 66
Modeling Hip-fape, 6
{Eoval Ure of Vasiable, 72
ZAR. Nubipie Clocks, 75
2s,
Bus.
220,
22,

202,
275

224

Cuarter 3

Comers

2472. Multiphase Cooks, 77
2173, With AsguehronooeProsstand Clee, 78
ZITA. With synchronous Preset and Clear, Bt
‘More on Blocking vs Now-bocking Assignments, 84
Fioetious, 88
Tasks, 9
Using Values xan! 2, 98
221.1, The Valuc x, 93
2202, The Val. 2
Gots Level Moseling, 97
Movin Trstaniation Statement, 98
223.1. Caing Predetined Blocks.
taming Csr bil Matipliers, 99
Insusxnng Csor-speetc Fip-ips, 101
tinad Designs, 10%

Modeling Examples 107

BM.
32
aa
34,
35,

36.
37

38.

3a,

Modeling Combinational Logic. 108

Modeling Sequentid Logie, 1140

Modeling « Memary. UT

‘Writing Roclean Bqpations, 113

Modeling a Fie Stace Machin

332, Moore FSM, Ll

352 Mealy ESM, 117

353, Bnoodkge States,
Using legers. 12
‘emg Parete Desens, (22

‘Modeling un Universal Shit Register, 127

Modeling an AL, 124

AIA. APasntiiced ALM, 124

372. ASiple ALU, 126

Modeling a Counter, 128

BAI. Binary Comer, 128

262, ptlaty Counter, 128

ACH Isha Cantar, 1

BRA. Gray Comer, 132

Modeling a Parameterized Adder, 133

ua
3.40, Modeling « Paracueerizci| Conparstor, 134
3.11. Modeling a Decode, 136
BALA. A Simple Desoder, 136
311.2, Binary Doooéer, 136
3113. Juhason Decade, 137
3.42, Modeling a Muldpleser, 139
S12, A Simple Rutsplster, 139
3122. A Parmotcrized Malpleser, 4
3.13, Modeling a Pasametarizad Pariey Generar, 141
3.14, Modeling a Thce-stow Gite, 143,
315, ACaunt Three I's Model, £4
3.16, A Factorial Model, 145
BAT. ARUART Model, 147
SLR, A Blackjack Mol, 153

CHAPTER A
Model Optimizations 157
44. Resource Allaation, 158
4.2. Common Subexpressions, 161
43. Moving Coxe, 162
44. Conon Factoring, 163,
45. Commutativity and Associnuity, 16¢
46. Omhoe Optimizations, 165
4.7, Flip-op and Latch Optimizations. 166
471, Avonlng gl, 166
472, Avonling lates, 167
44. Design Size, 168
Swall Design Syhesze Faster, 168
Hanuchy, 10
Macias a Sisto, 169

49. Using Pareuheses. 170

Charter 5
Verification 173
54. ATeat Bench, (74
52. Delayein Assigoment Statements, 176
53, Unconmected Ports, 178