UM10503 LPC43xx ARM Cortex-M4/M0 dual-core microcontroller

1416 Pages·2013·9.41 MB·English

UM10503
LPC43xx ARM Cortex-M4/M0 multi-core microcontroller
Rev. 1.7 — 17 October 2013 User manual
Document information
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Keywords LPC43xx, LPC4300, LPC4370, LPC4350, LPC4330, LPC4320, LPC4310,
LPC4357, LPC4353, LPC4337, LPC4333, LPC4327, LPC4325, LPC4323,
LPC4322, LPC4317, LPC4315, LPC4313, LPC4312, ARM Cortex-M4, ARM
Cortex-M0, SPIFI, SCT, USB, Ethernet, LPC4300 user manual, LPC43xx
user manual
Abstract LPC4300 user manual
UM10503
NXP Semiconductors
LPC43xx User manual
Revision history
Rev Date Description
1.7 20131017 LPC43xx User manual
Modifications: • 12-bit ADC (ADCHS) for parts LPC4370 added. See Chapter47.
• Table45 “LPC43xx part identification numbers” updated.
• BASE_APLL_CLK renamed to BASE_AUDIO_CLK in Chapter12 “LPC43xx Clock Generation Unit
(CGU)”, Chapter13 “LPC43xx Clock Control Unit (CCU)”, Chapter10 “LPC43xx Configuration
Registers (CREG)”, and Chapter43 “LPC43xx I2S interface”.
• Core M0SUB added for parts LPLC4370. See Chapter2 “LPC43xx Multi-Core configuration and
Inter-Process Communication (IPC)”, Chapter12 “LPC43xx Clock Generation Unit (CGU)”,
Chapter13 “LPC43xx Clock Control Unit (CCU)”, Chapter10 “LPC43xx Configuration Registers
(CREG)”, Chapter14 “LPC43xx Reset Generation Unit (RGU)”, and Chapter3 “LPC43xx Memory
mapping”.
• Power-down mode with M0SUB SRAM maintained added for parts LPC4370. See Chapter11
“LPC43xx Power Management Controller (PMC)” and Table115.
• AES speed corrected. See Section7.2.
• Bit description of register CREG5 corrected. Bits 9:0 changed to reserved. Use bits 12:10 for
disabling JTAG. See Section10.4.3 “CREG5 control register”.
• Description of the RESET pin updated in Section15.2 “Pin description”.
• Use of EMC_CLK pins clarified for SDRAM devices. See Section22.2.
• Pin description of the RESET pin updated. See Chapter15
• Pin description of pins SD_VOLTD[2:0] updated in Table352.
• Add bits 20 (BOD reset) and 21 (reset after wake-up from deep power-down) to the event router
registers. See Table80, Table83 to Table91.
• Table200 “SD/MMC delay register (SDDELAY, address 0x4008 6D80) bit description” added.
• USB driver code listing corrected. See Section26.5 “USB API”.
• Register RESET_EXT_STAT4 removed. See Table167.
• SDRAM address mappings added in Table430.
• Device MX25L6435EM2I-10G added to Table24 “QSPI devices supported by the boot code and the
SPIFI API”.
• Table4 “Ordering options” corrected. ULPI not available on 144-pin and 100-pin packages.
• Editorial updates to Section5.3.5 “Boot image creation” and Figure16 “Image encryption flow”
added.
• Editorial edits to Chapter7 “LPC43xx Security API”. Section “CMAC using AES hardware
acceleration” removed.
• VADC replaced by ADCHS throughout the document.
• Section12.2.1 “Configuring the BASE_M4_CLK for high operating frequencies” corrected to ensure
safe operation of the clock ramping procedure.
• Figures and tables in Section43.7.2 “I2S operating modes” corrected.
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Revision history …continued
Rev Date Description
Modifications: • LPC4320 and LPC4310 part IDs corrected. See Table45 “LPC43xx part identification numbers” and
the LPC4350/30/20/10 errata sheet.
• Description of word1 of the part id corrected. See Table45 “LPC43xx part identification numbers”.
• General description of the OTP updated. See Section4.3.
• General description of the AES updated. See Section7.3.
• Figure14 “Boot process for parts without flash” updated.
• Figure115 “Repetitive Interrupt Timer (RIT) block diagram” corrected.
• Details about encryption of the image header added in Section5.3.4 “Boot image header format”.
• Figure14 “Boot process for parts without flash” corrected. SPI(SSP) boot requires image header.
• Bit description of Table378 “Debounce Count Register (DEBNCE, address 0x4000 4064) bit
description” updated. Host clock is the SD_CLK clock.
• Security features updates. FIPS compliancy added. See Section7.2.
• ISP mode added to Figure14 “Boot process for parts without flash”.
• Reset values of the EEPROM RWSTATE and WSTATE registers updated. See Table1153.
• AES API function offsets corrected. See Table73.
• Part MX25L8006EM2L-12GMX25L8035E, MX25L1633E, MX25L3235E, MX25L6435E,
MX25L12835F, MX25L25635F added to list of devices supported for SPIFI boot. See Table24.
1.6 20130125 LPC43xx user manual.
Modifications: • SGPIO-DMA connections clarified. See Figure10 and Figure11.
• SGPIO location corrected in Figure1 and Figure3.
• SGPIO added to DMA master 0. See Section19.4 and Section18.4.1.
• GPIO group interrupt wake-up from power-down modes corrected in Section17.3.2. Only wake-up
from sleep mode supported.
• Section5.3.6.4.1 “Supported QSPI devices” moved to Chapter5 “LPC43xx Boot ROM”.
• SPIFI register map and register descriptions added in Chapter22 “LPC43xx SPI Flash Interface
(SPIFI)”.
• Bit description of Table987 “CAN error counter (EC, address 0x400E2008 (C_CAN0) and 0x400A
4008 (C_CAN1)) bit description” corrected.
• Bit clock calculation and bit description corrected in Section43.6.1.4 “CAN bit timing register”.
1.5 20121203 LPC43xx user manual.
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Revision history …continued
Rev Date Description
Modifications • Statement regarding the connection between sampling pin P2_7 and the watchdog timer overflow bit
is incorrect and was removed in Section47.4.1 “Sampling of pin P2_7” and Figure176 “Boot process
flowchart for LPC43xx parts with flash”.
• SCT alias register locations corrected in Table648.
• IRC accuracy corrected for flash-based parts. See Section1.2.
• SCT with dither engine added for flash-based parts.
• SGPIO DMA connections added in Table45 “DMA mux control register (DMAMUX, address 0x4004
311C) bit description”.
• Section26.6.2 “MAC Frame filter register” updated to include hash filter option.
• Section26.7.1 “Hash filter” with examples added.
• Description of the I2C MASK register clarified (see Section44.7.10).
• Description of the I2C slave address updated in Section44.7.8.
• UART1 TER register location and bit description corrected. See Table902.
• Polarity of the DMACSYNC bit in the GPDMA SYNC register corrected (see Table285).
• SGPIO pattern match example corrected. See Section18.7.3.
• OTP API function table corrected. Location 0x1C is reserved. See Table16.
• SPIFI data rate and maximum clock corrected to SPIFI_CLK = 104 MHz and 52 MB/s.
• Parts LPC433x, LPC432x, and LPC431x added.
• The following changes were made on the TFBGA180 pinout in Table128:
– P1_13 moved from ball D6 to L8.
– P7_5 moved from ball C7 to A7.
– PF_4 moved from ball L8 to D6.
– RESET moved from ball B7 to C7.
– RTCX2 moved from ball A7 to B7.
– Ball G10 changed from VSS to VDDIO.
• Section49.9 “JTAG TAP Identification” updated.
• EMC Configuration register, bit 8 changed to reserved. See Table356 “EMC Configuration register
(CONFIG - address 0x40005008) bit description”.
• Dual-core power-down modes added to Chapter10 “LPC43xx Power Management Controller
(PMC)”.
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Revision history …continued
Rev Date Description
Modifications: • ETM time stamping feature not implemented. See Chapter49.
• Bit 0 in the RGU RESET_STATUS0 register changed to reserved. Section13.5.1 “Determine the
cause of a core reset” added.
• Micron part N25Q256 removed from the list of devices supported by the SPIFI boot ROM driver and
API. (See Table387 “QSPI devices not supported by the boot code”.) Section22.6 updated.
• Part S25FL129P0XNFI01 added to the list of devices supported by the SPIFI boot ROM driver.
• SGPIO register descriptions for CTRL_ENABLED and CTRL_DISABLED registers updated (see
Table230 and Table231).
• Section21.7.5 “Dynamic Memory Refresh Timer register” register description updated.
• Description of the Motor control PWM INVDC bit updated in Table734 “MCPWM Control read
address (CON - 0x400A0000) bit description”.
• Description of the Alarm timer PRESETVAL bit updated in Table799 “Preset value register (PRESET
- 0x4004 0004) bit description”.
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC is connected to
ADC0 and ADC1. See Table128, Table129, Table1040, and Section15.1.
• Description of extra status bits added to Table568 “DMA Status register (DMA_STAT, address
0x4001 1014) bit description”.
• Use of lower SPIFI memory clarified in Table384 “SPIFI flash memory map”.
• Description of DAC DMA_ENA bit clarified in Table1054 “D/A Control register (CTRL - address
0x400E1004) bit description”.
• Pseudo-code for PLL registers updated by code snippets from LPC43xx sample code in Chapter11.
• Reset delay clock cycles explained in Section13.4.1 “RGU reset control register”.
1.4 20120903 LPC43xx user manual.
Modifications: • SSP0 boot pin functions corrected in Table18 and Table19. Pin P3_3 = SSP0_SCK, pin P3_6 =
SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• CLKMODE3 removed from the SCT. Bit value CLKMODE = 0x3 changed to reserved in Table647
“SCT configuration register (CONFIG - address 0x4000 0000) bit description”.
• SWD mode removed for ARM Cortex-M0.
• Details for GIMA clock synchronization added in Section16.3.2.
• RESET_EXT_STATUS0 register removed in Chapter13.
• Reset value of BASE_SAFE_CLK register changed to R (read-only) in Table84.
• Reset delay values corrected in Figure31 “RGU Reset structure”.
• RGU reset values corrected in Table113 “Register overview: RGU (base address: 0x4005 3000)”.
• Editorial updates in Chapter18 “LPC43xx Serial GPIO (SGPIO)”.
• POR reset value of the event router STATUS register corrected in Table31 and Table37.
• USB boot mode updated: 12 MHz external crystal required. See Section5.3.5.5.
• IAP invoke call entry pointer clarified in Section46.8.
• EMC memory data and control lines clarified for the LQFP208 package in Table349.
• Figure11 updated to include boot process for AES capable parts.
• Editorial updates.
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Revision history …continued
Rev Date Description
1.3 20120706 LPC43xx user manual.
Modifications: • Description of USB CDC device class updated in Section25.5.26 “USBD_API_INIT_PARAM” and
Section25.5.27 “USBD_CDC_API”.
• Section24.7.1 “Susp_CTRL module” added for USB1.
• Section23.11 “USB power optimization” updated.
• Table20 “Boot image header use” added.
• AES only available for LPC43Sxx parts.
• Bank, Row, Column addressing for SDRAM devices added in Table373.
• Parts LPC4337 and LPC4333 added.
1.2 20120608 LPC43xx user manual.
Modifications: • Syncflash removed from Chapter21.
• Parameter t updated in Section5.3.6.
b
• Parameters for ISP/IAP command “Copy RAM to flash” updated (Table1031 and Table1044).
• Part IDs updated in Table1036; also see Errata note ES_LPC43X0_A.
• Description of CTRL_DISABLE register updated (see Table230).
• Table215 “SGPIO multiplexer” corrected.
• Flash accelerator register waitstate values added (see Table46 and Table47).
• Programming procedure for the SDRAM mode register added in Section21.8.5.
• Clock ramp-up procedures for core clock added in Section11.2.1.
• Description of the event router updated (see Section8.3).
1.1 20120510 LPC43xx user manual.
Modifications: • Reset value of the ETB bit in the ETBCFG register changed to one (see Table48).
• UART1 FIFOLVL register removed.
• Chapter46 “LPC43xx flash programming/ISP and IAP” added.
• OTP memory bank 0 changed to reserved.
• Hardware IP checksum feature removed from ethernet block.
• USB frame length adjust register added (see Table54 and Table55; for parts with on-chip flash only).
• Flash accelerator control registers added (see Table46 and Table47; for parts with on-chip flash
only).
• Support for SAMPLE pin added to the CREG0 register (Table42).
• Chapter47 “LPC43xx EEPROM memory” added (for parts with on-chip flash only).
• SDRAM low-power mode removed in Chapter21.
• Motor control PWM hardware noise filtering removed.
• Description of the QEI register VEL corrected.
• Chapter41 “LPC43xx I2S interface” updated.
• Remove condition RTC_ALARM = LOW on reset for entering debug mode.
• Ethernet chapter updated: PPS and auxiliary timestamp features removed.
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Revision history …continued
Rev Date Description
Modifications: • Chapter36 “LPC43xx Event monitor/recorder” added (for parts with on-chip flash only).
• Connection of USB0_VBUS/USB1_VBUS signals added (Section23.5.1).
• Description of ADC GDR register updated (Section44.6.2).
• Pin reset states updated in Table128 and Table129.
• SCT register map updated in Table645.
• Changed maximum clock frequency for SWD and ETB access to 120 MHz in Chapter48.
• Reduced and normal power modes removed in Chapter10.
• AES encryption option added in Table22 (parts LPC43Sxx only).
• SGPIO register names and descriptions updated.
• Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.
• Update procedure Section23.10.8.1.2 “Setup packet handling using the trip wire mechanism”.
• Polarity of bit OUTSEL in the SCT EVCTRL register swapped (see Table670).
• Bit 9 (JTAG enable for the M0 co-processor) added to the CREG5 register (Table44).
• Description of CCU Auto mode updated (see Section12.5.3).
• Maximum power consumption in the USB Suspended state corrected according to USB 2.0 ECN
specification (see Section23.11.2).
• LQFP100 package removed.
1 20111212 Preliminary LPC43xx user manual.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Chapter 1: Introductory information
Rev. 1.7 — 17 October 2013 User manual
1.1 Introduction
The LPC43xx are ARM Cortex-M4 based microcontrollers for embedded applications
which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 kB of
SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT)
and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,
Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.
The LPC43xx operate at CPU frequencies of up to 204 MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The LPC43xx contain one or two ARM Cortex-M0 processors to share computing tasks
with the main ARM Cortex-M4 processor. All processors can serve peripherals.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,
designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz
performance with a simple instruction set and reduced code size.
1.2 Features
• Cortex-M4 Processor core
– ARM Cortex-M4 processor, running at frequencies of up to 204MHz.
– ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
– ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
– Hardware floating-point unit.
– Non-maskable Interrupt (NMI) input.
– JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four
watch points.
– Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
– System tick timer.
• Cortex-M0 Processor core (all LPC43xx parts)
– ARM Cortex-M0 processor capable of off-loading the main ARM Cortex-M4
processor.
– Running at frequencies of up to 204 MHz.
– JTAG and built-in NVIC.
• Cortex-M0 Processor subsystem core (LPC4370 parts only)
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Chapter 1: Introductory information
– ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on
a separate AHB multilayer matrix with direct access to 2 kB + 16kB of SRAM.
– Connected via a core-to-core bridge to the main AHB multilayer matrix and the
main ARM Cortex-M4 processor.
– Running at frequencies of up to 204 MHz.
– JTAG and built-in NVIC.
• On-chip memory (flashless parts)
– Up to 264 kB SRAM for code and data use.
– Additional 18 kB of SRAM for direct access by the M0 subsystem core (LPC4370
only).
– Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
– 64 kB ROM containing boot code and on-chip software drivers.
– General-purpose One-Time Programmable (OTP) memory.
• On-chip memory (parts with on-chip flash)
– Up to 1 MB on-chip dual bank flash memory with flash accelerator.
– 16 kB on-chip EEPROM data memory.
– 136 kB SRAM for code and data use.
– Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
– 64 kB ROM containing boot code and on-chip software drivers.
– General-purpose One-Time Programmable (OTP) memory.
• Configurable digital peripherals
– Serial GPIO (SGPIO) interface.
– State Configurable Timer (SCT) subsystem on AHB.
– Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
• Serial interfaces
– Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB
per second.
– 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping and advanced
time stamping (IEEE 1588-2008 v2).
– One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
– One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
– USB interface electrical test software included in ROM USB stack.
– One 550 UART with DMA support and full modem interface.
– Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
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Chapter 1: Introductory information
– Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge.
– Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
– One SPI controller.
– One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1Mbit/s.
– One standard I2C-bus interface with monitor mode and with standard I/O pins.
– Two I2S interfaces, each with DMA support and with one input and one output.
• Digital peripherals
– External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
– LCD controller with DMA support and a programmable display resolution of up to
1024H  768V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct
pixel mapping.
– Secure Digital Input Output (SD/MMC) card interface.
– Eight-channel General-Purpose DMA (GPDMA) controller can access all
memories on the AHB and all DMA-capable AHB slaves.
– Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
– GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
– Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
– Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
– Four general-purpose timer/counters with capture and match capabilities.
– One motor control Pulse Width Modulator (PWM) for three-phase motor control.
– One Quadrature Encoder Interface (QEI).
– Repetitive Interrupt timer (RI timer).
– Windowed watchdog timer (WWDT).
– Ultra-low power Real-Time Clock (RTC) on separate power domain with 256bytes
of battery powered backup registers.
– (Parts with on-chip flash only): Event recorder with three inputs to record event
identification and event time; can be battery powered.
– Alarm timer; can be battery powered.
• Analog peripherals
– One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
– Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
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