Ultra-Low Power Wireless Technologies for Sensor Networks

191 Pages·2007·7.604 MB·English

by  Brian Otis, Jan Rabaey (auth.)

Ultra-Low Power Wireless
Technologies for Sensor

Networks
SERIES ON INTEGRATED CIRCUITS AND SYSTEMS

Anantha Chandrakasan, Editor
Massachusetts Institute of Technology
Cambridge, Massachusetts, USA
Published books in the series:

Ultra-Low Power Wireless Technologies for Sensor Networks
Brian Otis and Jan Rabaey
2007, ISBN 978-0-387-30930-9

Sub-threshold Design for Ultra Low-Power Systems
Alice Wang, Benton H. Calhoun, and Anantha Chandrakasan
2006, ISBN 0-387-33515-3

High Performance Energy Efficient Microprocessor Design
Vojin Oklibdzija and Ram Krishnamurthy (Eds.)
2006, ISBN 0-387-28594-6

Abstraction Refinement for Large Scale Model Checking
Chao Wang, Gary D. Hachtel, and Fabio Somenzi
2006, ISBN 0-387-28594-6

A Practical Introduction to PSL
Cindy Eisner and Dana Fisman
2006, ISBN 0-387-35313-5

Thermal and Power Management of Integrated Circuits
Arman Vassighi and Manoj Sachdev
2006, ISBN 0-398-25762-4
Leakage in Nanometer CMOS Technologies
Siva G. Narendra and Anantha Chandrakasan
2005, ISBN 0-387-25737-3

Statistical Analysis and Optimization for VLSI: Timing and Power
Ashish Srivastava, Dennis Sylvester and David Blaauw
2005, ISBN 0-387-26049-8
Brian Otis and Jan Rabaey

Ultra-Low Power Wireless
Technologies for Sensor
Networks
Brian Otis
University of Washington
Department of Electrical Engineering
Seattle, WA, USA

Jan Rabaey
University of California, Berkeley
Department of Electrical Engineering and Computer Science
Berkeley, CA, USA

Ultra-Low Power Wireless Technologies for Sensor Networks

Library of Congress Control Number: 2006936495

ISBN 0-387-30930-6 e-ISBN 0-387-49313-1
ISBN 978-0-387-30930-9 e-ISBN 978-0-387-49313-8

Printed on acid-free paper.

© 2007 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without the written
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Table of Contents
List of Figures................................................. ix
List of Tables .................................................. xv
1 WIRELESS SENSOR NETWORKS ....................... 1
1.1 System Requirements .................................... 3
1.2 Energy Scavenging....................................... 4
1.3 RF Transceiver Requirements ............................. 5
1.3.1 Power Consumption ............................... 5
1.3.2 Datarate ......................................... 5
1.3.3 Range ........................................... 6
1.3.4 Sensitivity........................................ 6
1.3.5 Turn-On Time .................................... 7
1.3.6 Integration/Power Tradeoff ......................... 8
1.4 Contributions of this Book................................ 9
2 LOW POWER CMOS DESIGN FOR RADIO
FREQUENCIES........................................... 13
2.1 Weak Inversion RF CMOS................................ 13
2.2 MEMS Background...................................... 15
2.3 Circuit Proof-of-Concept I: 300µW Pierce Oscillator ......... 19
2.4 Circuit Proof-of-Concept II: Differential 300µW BAW-Based
Oscillator............................................... 24
2.4.1 Analysis/Design................................... 24
2.4.2 Experimental Results (1.9GHz) ..................... 28
2.4.3 Experimental Results (2.4GHz) ..................... 33
2.5 System Proof-of-Concept: Energy Scavenging Transmit Beacon 35
3 TWO CHANNEL BAW-BASED TRANSCEIVER......... 41
3.1 Architecture ............................................ 41
3.2 LNA Design ............................................ 42
vi Table of Contents
3.3 CSA Analysis and Design ................................ 44
3.3.1 Active Inductor ................................... 44
3.3.2 Standalone RF Amplifier ........................... 47
3.3.3 In-Situ RF Amplifier............................... 51
3.4 RF Detector Analysis and Design.......................... 53
3.5 Transmitter Architecture and Design....................... 55
3.6 Experimental Results .................................... 55
3.6.1 Implementation ................................... 55
3.6.2 Receiver.......................................... 56
3.6.3 Transmitter ...................................... 57
3.7 Conclusions............................................. 59
4 SUPER-REGENERATIVE RECEIVER DESIGN ......... 61
4.1 History of the Super-Regenerative Receiver ................. 61
4.2 Motivation ............................................. 62
4.3 Architecture ............................................ 65
4.4 Analysis................................................ 66
4.4.1 Operation ........................................ 66
4.4.2 Super-Regenerative Gain ........................... 66
4.4.3 Super-Regenerative Bandwidth...................... 68
4.4.4 Quench Frequency Limitations...................... 71
4.5 LNA/Oscillator Design................................... 72
4.6 Additional Circuitry ..................................... 74
4.7 Experimental Results .................................... 74
4.7.1 Board Design ..................................... 74
4.7.2 Testing Methodology .............................. 74
4.7.3 Results........................................... 75
4.8 Discussion .............................................. 78
5 FULLY INTEGRATED SUPER-REGENERATIVE
TRANSCEIVER .......................................... 81
5.1 Architecture ............................................ 81
5.2 RF Front-End Circuit Design ............................. 81
5.3 Pulse Width Demodulator................................ 83
5.3.1 Filter Specifications................................ 83
5.3.2 Filter Synthesis and Design......................... 85
5.4 Capacitance Tuning ..................................... 88
5.5 Chip Implementation .................................... 89
5.6 Measured Results........................................ 90
5.6.1 Serial Interface.................................... 90
5.6.2 RF Front-End .................................... 91
5.6.3 Temperature Compensation ........................ 96
5.6.4 Baseband ........................................ 98
5.6.5 Link Demonstration ............................... 99
5.7 Discussion .............................................. 99
Table of Contents vii
6 INTEGRATION TECHNIQUES ..........................103
6.1 Silicon Reference Clocks..................................103
6.1.1 Silicon Resonator Background.......................104
6.1.2 Circuit Analysis and Design ........................106
6.2 Flip-Chip Packaging .....................................112
6.2.1 Oscillator Flip-Chip ...............................113
6.2.2 Super-Regenerative Flip-Chip.......................114
6.3 Conclusions.............................................116
7 ULTRA-LOW POWER RADIO IN A PACKAGE USING
ULTRA-WIDE BAND TECHNOLOGY ...................117
7.1 Introduction ............................................117
7.2 UWB for Sensor Networks ................................118
7.2.1 Air Interface Definition ............................118
7.2.2 UWB System Implementation ......................120
7.3 UWB Radio Design......................................122
7.3.1 UWB Pulse Generator Design ......................123
7.3.2 UWB Receiver Design..............................129
7.4 Heterogeneous Integration ................................134
7.4.1 Introduction ......................................134
7.4.2 Layered Design Approach...........................135
7.4.3 Elementary Application.............................140
8 LOW ENERGY WIRELESS COMMUNICATION ........143
8.1 Introduction ............................................143
8.2 Fundamental Energy Requirements of Wireless
Communication .........................................143
8.2.1 Theoretical System Energy Limits ...................146
8.3 Low Energy Transceiver Design ...........................149
8.3.1 Modulation Scheme................................149
8.3.2 Minimizing Overhead Power ........................153
8.3.3 Receiver Noise Factor and Passive Voltage Gain.......157
8.3.4 Efficient PAs with Low Power Output................162
8.4 A Low Energy 2.4GHz Transceiver.........................165
8.5 Summary and Conclusions................................166
9 CONCLUSIONS...........................................171
References.....................................................175
Index..........................................................181
List of Figures
1.1 Hardware blocks for sub-mW sensor network implementations.. 2
1.2 Radio range for receiver with a -70dBm sensitivity............ 7
2.1 The transconductance efficiency is plotted vs. the inversion
coefficient. (Courtesy of Nathan Pletcher) ................... 14
2.2 Simplified circuit equivalent model of a BAW resonator........ 17
2.3 Simplified oscillator schematic ............................. 20
2.4 Optimization of BAW resonator area. Three curves are shown
with various values of C =C ............................. 22
1 2
2.5 Photograph of the CMOS/BAW prototype oscillator.......... 22
2.6 Measured phase noise performance of the oscillator ........... 23
2.7 Schematic of differential oscillator .......................... 26
2.8 Simulation results of oscillator loopgain for varying
values of C ............................................. 26
s
2.9 Loopgain detail at oscillation frequency ..................... 27
2.10 Differential oscillator layout detail .......................... 28
2.11 Differential oscillator COB assembly ........................ 29
2.12 Measured differential oscillator phase noise .................. 30
2.13 Measured differential oscillator start-up transient............. 31
2.14 Measured temperature coefficient of oscillation for two CMOS
oscillators ............................................... 32
2.15 ISM implementation of differential oscillator ................. 33
2.16 ISM differential oscillator transient output................... 34
2.17 ISM differential oscillator phase noise ....................... 35
2.18 RF Transmitter COB implementation....................... 37
2.19 Transmit beacon implementation ........................... 38
2.20 RF transmit beacon under low light conditions............... 39
3.1 Block diagram of the two-channel transceiver ................ 42
3.2 Simplified receiver front-end schematic ...................... 43
3.3 Measured S-parameters of the LNA test structure ............ 44
3.4 Schematic of active choke inductor structure ................. 45
x List of Figures
3.5 Standalone RF amplifier schematic ......................... 48
3.6 Simulated S and NF of the RF Amplifier .................. 49
21
3.7 Photograph of standalone RF amplifier...................... 50
3.8 Measured S-Parameters of the RF Amplifier ................. 50
3.9 Schematic of in-situ RF amplifier........................... 52
3.10 Schematic of the RF Detector.............................. 53
3.11 Measured conversion gain of the envelope detector............ 54
3.12 Block diagram of the transmitter ........................... 55
3.13 OOK Transmitter Schematic............................... 56
3.14 Photograph of the transceiver implementation................ 57
3.15 Normalized receiver gain of both channels ................... 58
3.16 Receiver enable-to-data start-up time ....................... 58
3.17 Breakdown of the receiver current consumption (mA) ......... 59
3.18 Transmitter modulation start-up time....................... 60
4.1 Vintage 1940s two-tube super-regenerative detector [1].
Reprinted with permission of Cambridge Press ............... 62
4.2 Conceptual diagram of super-regenerative detection........... 63
4.3 Modes of super-regenerative operation. a) Linear, b)
Logarithmic, c) RF Input ................................. 64
4.4 Block diagram of proposed super-regenerative transceiver...... 65
4.5 Startup of RF oscillator in the presence of noise.............. 67
4.6 Schematic of super-regenerative front-end ................... 73
4.7 Die photograph of the super-regenerative receiver............. 75
4.8 Measured S magnitude of super-regenerative receiver........ 76
11
4.9 Super-regenerative eye diagram in the presence of a -80dBm
signal ................................................... 76
4.10 Measuredsignal-dependentgainresponseofsuper-regenerative
receiver ................................................. 77
4.11 Supply voltage dependence of super-regenerative receiver ...... 78
5.1 Simplified schematic of the current source DAC .............. 82
5.2 CAD layout of current source DAC ......................... 83
5.3 Simulated input/output waveforms of the demodulator........ 84
5.4 System-level simulation of pulse-width demodulator........... 85
5.5 Pulse width demodulator filter ladder ....................... 86
5.6 Schematic of the filter transconductor....................... 86
5.7 Layout of the filter OTA .................................. 87
5.8 Layout of the pulse width demodulator...................... 88
5.9 Schematic of binary weighted switched capacitor tuning array.. 89
5.10 Micrograph of the assembled integrated transceiver ........... 90
5.11 Measured leakage current and power of digital control block ... 91
5.12 DAC DNL Measurement .................................. 92
5.13 DAC INL Measurement ................................... 92
5.14 Incremental frequency shift over all codes.................... 93
List of Figures xi
5.15 Switched capacitor frequency tuning of receiver .............. 94
5.16 Measuredsuper-regenerativeoscillatoramplitudevs.frequency
code .................................................... 94
5.17 Measured phase noise of detector oscillator over tuning range .. 95
5.18 Magnitude of receiver S .................................. 96
11
5.19 Receiver selectivity profile for two bias current levels.......... 97
5.20 Temperature compensation of BAW-based receiver ........... 98
5.21 Measured frequency response of baseband filter at the high
and low bandwidth settings................................ 99
5.22 Measured ripple of the pulse-width demodulator at quench
frequencies of 10kHz, 30kHz, and 100kHz....................100
5.23 Power breakdown of the fully integrated super-regenerative
receiver .................................................100
6.1 Cross-sectional process sequence. Reprinted with permission
of IEEE .................................................105
6.2 Simulation of the coupled wineglass and lam´e mode resonators .106
(a) Coupled wineglass mode resonator.....................106
(b) Coupled lame mode resonator.........................106
6.3 Conceptual schematic of 16MHz clock oscillator ..............107
6.4 Schematic of 16MHz clock oscillator ........................108
6.5 Gain (Ω) of the transimpedance amplifier ...................109
6.6 Schematic of amplitude control OTA........................110
6.7 Simulation of amplitude control loop convergence.............111
6.8 Layout of 16MHz reference clock ...........................112
6.9 BAW flipped onto a 0.18µm CMOS oscillator ................114
6.10 SEM image of super-regenerative flip-chip ...................114
(a) BAW flip-chip ......................................114
(b) Detail of BAW/CMOS interface.......................114
6.11 Coverage of planar inductor by BAW resonator ..............115
6.12 Super-regenerative S : Effect of flip-chip proximity on planar
11
inductors................................................116
7.1 Impact of parameter variations on the PSD (a) of the gaussian
pulse, (b) on the triangular pulse ...........................119
7.2 Impulse-based ultra-wideband transmitter architecture .......120
7.3 Integrator circuit to generate the ramping slope of the
triangular signal .........................................122
7.4 Block diagram of the pulse generator .......................123
7.5 PPM modulator circuit ...................................124
7.6 The triangular pulse generator circuit ......................125
7.7 The three-stages ring oscillator ............................126
7.8 Multiplier circuit consisting of a switching differential pair
whose tail current is modulated by the triangular waveform ...127
7.9 Spectrum of the current pulse for ±10% variation of β ........128