Timing Analysis and Simulation for Signal Integrity Engineers PDF
Preview Timing Analysis and Simulation for Signal Integrity Engineers
Timing Analysis and Simulation for Signal Integrity Engineers Timing Analysis and Simulation for Signal Integrity Engineers Greg Edlund An Imprint of Pearson Education Upper Saddle River,NJ • Boston • Indianapolis • San Francisco New York • Toronto • Montreal • London • Munich • Paris • Madrid Cape Town • Sydney • Tokyo • Singapore • Mexico City Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this book,and the publisher was aware of a trademark claim,the designations have been printed with initial capital letters or in all capitals. The author and publisher have taken care in the preparation of this book,but make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is assumed for incidental or consequential damages in connection with or arising out of the use of the information or programs contained herein. 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To gain 45-day Safari Enabled access to this book: • Go to http://www.prenhallprofessional.com/safarienabled. • Complete the brief registration form. • Enter the coupon code TJNR-YCRL-WQ2V-2GLN-2KY9. If you have difficulty registering on Safari Bookshelf or accessing the online edition,please e-mail customer-service@safaribooks- online.com. Visit us on the Web:www.prenhallprofessional.com Library of Congress Cataloging-in-Publication Data Edlund,Greg. Timing analysis and simulation for signal integrity engineers / Greg Edlund. p. cm. ISBN 0-13-236504-9 (hbk. :alk. paper) 1. Timing circuits—Design and construction. 2. Digital electronics—Design and construction. 3. Signal processing—Digital techniques. I. Title. TK7874.65E36 2007 621.3815—dc22 2007030307 Copyright ©2008 Pearson Education,Inc. All rights reserved. Printed in the United States of America. This publication is protected by copyright,and permission must be ob- tained from the publisher prior to any prohibited reproduction,storage in a retrieval system,or transmission in any form or by any means,electronic,mechanical,photocopying,recording,or likewise. For information regarding permissions,write to: Pearson Education,Inc. Rights and Contracts Department 501 Boylston Street,Suite 900 Boston,MA 02116 Fax (617) 671 3447 ISBN-13:978-0-132-36504-8 ISBN-10:0-13-236504-9 Text printed in the United States on recycled paper at Courier Westford,Westford Massachusetts. First printing October,2007 Editor-in-Chief:Mark Taub Indexer:Lisa Stumpf Editorial Assistant:Michelle Housley Acquisitions Editor:Bernard Goodwin Proofreader:Williams Woods Publishing Cover Designer:Alan Clements Managing Editor:Gina Kanouse Technical Reviewers:Bob Haller,Lynne Composition:Bronkella Publishing Senior Project Editor:Kristy Hart Green,Mike Resso,Andy Martwick, Copy Editor:Water Crest Publishing Jim Peterson “Our planet is a lonely speck in the great enveloping cosmic dark. In our obscurity,in all this vastness,there is no hint that help will come from elsewhere to save us from ourselves.” “It has been said that astronomy is a humbling and character building experience. There is perhaps no better demonstration of the folly of human conceits than this distant image of our tiny world. It underscores our responsibility to deal more kindly with one another,and to preserve and cherish the pale blue dot,the only home we’ve ever known.” —Carl Sagan,from a public lecture delivered on October 13,1994,at Cornell University This page intentionally left blank Contents Preface xiii Acknowledgments xvi About the Author xix About the Cover xx 1 Engineering Reliable Digital Interfaces 1 A Sadly Familiar Tale 3 Power On 4 The Long Reach of Legacy Design 6 Reflections on a Near Disaster 8 Motivations to Develop a Simulation Strategy 9 The Boundaries of Simulation Space 10 vii viii Timing Analysis and Simulation for Signal Integrity Engineers 2 Chip-to-Chip Timing 13 Root Cause 14 CMOS Latch 14 Timing Failures 18 Setup and Hold Constraints 19 Common-Clock On-Chip Timing 22 Setup and Hold SPICE Simulations 25 Timing Budget 26 Common-Clock IO Timing 28 Common-Clock IO Timing Using a Standard Load 32 Limits of the Common-Clock Architecture 38 3 Inside IO Circuits 39 CMOS Receiver 40 CMOS Differential Receiver 42 Pin Capacitance 43 Receiver Current-Voltage Characteristics 45 CMOS Push-Pull Driver 46 Output Impedance 48 Output Rise and Fall Times 49 CMOS Current Mode Driver 51 Behavioral Modeling of IO Circuits 53 Behavioral Model for CMOS Push-Pull Driver 54 Behavioral Modeling Assumptions 56 Tour of an IBIS Model 56 IBIS Header 61 IBIS Pin Table 61 IBIS Receiver Model 62 IBIS Driver Model 63 Behavioral Modeling Assumptions (Reprise) 65 Comparison of SPICE and IBIS Models 66 Accuracy and Quality of IO Circuit Models 68 Contents ix 4 Modeling 3D Discontinuities 73 Beyond Transmission Lines 74 Finite Difference Time Domain Method 75 Solo Flight in a 3D Field Solver 79 Coaxial Transmission Line 80 Boundary Conditions 82 Waveguide Ports 83 Stimulus Function 84 Mesh Density 85 Running the Solver 86 Port Signals 87 S-Parameters 88 Energy 89 Field Visualization 91 Coaxial Discontinuity 94 Formation of Reflection 96 S-Parameters and Their Explanation 97 5 Practical 3D Examples 101 Coupled Differential Vias 102 Mechanical Drawings 103 Ports 106 Mesh Density 108 Sanity Check 113 Documentation 114 Pre-Flight Checklist 116 Land Grid Array Connector 118 Mechanical Trade-Offs 120 Electrical Characterization 120 3D Modeling Decisions 122 Test Card Design 125 Model-to-Hardware Correlation 128
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