Time-interleaved Analog-to-Digital Converters

147 Pages·2011·2.85 MB·English

by  Simon Louwsma

Time-interleaved Analog-to-Digital Converters
ANALOGCIRCUITSANDSIGNALPROCESSINGSERIES
ConsultingEditor:MohammedIsmail.OhioStateUniversity
Forothertitlespublishedinthisseries,goto
www.springer.com/series/7381
Simon Louwsma (cid:2) Ed van Tuijl (cid:2) Bram Nauta
Time-interleaved
Analog-to-Digital
Converters
SimonLouwsma BramNauta
AxiomIC MESA+Institute
Colosseum28 UniversityofTwente
Enschede,7521PT P.O.Box217
Netherlands Enschede,7500AE
[email protected] Netherlands
[email protected]
EdvanTuijl
AxiomIC/UniversityofTwente
Colosseum28
Enschede,7521PT,
Netherlands
[email protected]
SeriesEditors:
MohammedIsmail MohamadSawan
205DreeseLaboratory ElectricalEngineeringDepartment
DepartmentofElectricalEngineering ÉcolePolytechniquedeMontréal
TheOhioStateUniversity Montréal,QC,Canada
2015NeilAvenue
Columbus,OH43210,USA
ISBN978-90-481-9715-6 e-ISBN978-90-481-9716-3
DOI10.1007/978-90-481-9716-3
SpringerDordrechtHeidelbergLondonNewYork
LibraryofCongressControlNumber:2010935602
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“Everythingshouldbemadeassimpleaspossible,butnotsimpler.”
—AlbertEinstein
Preface
This book describesthe research carried outby our PhD studentSimonLouwsma
at the University of Twente, The Netherlands in the field of high-speed Analog-
to-Digital (AD) converters. AD converters are crucial circuits for modern systems
whereinformationisstoredorprocessedindigitalform.Duetoincreasingdatarates
andfurtherdigitizationofsystems,thedemandsontheADconvertersareincreasing
inbothsample-rateandnumberofbits.
AfastandaccurateADconvertercombinedwithdigitalsignalprocessingoffers
an attractive alternative for the analog signal chain still present in many actual re-
ceivers.Thisbookoffersanexplorationoffundamentalandpracticallimitsofhigh
speedADconversion,aimingatastepforwardinnumberofbitsandsample-rate,
whilekeepingthepowerconsumptionlow.
Toachievehighperformance,atechniquecalledtimeinterleavingisused.Time
interleavingistheanalogequivalentofparallelprocessinginthedigitaldomain.To
implementthis,insteadofasingleTrack-and-Hold(T&H),weuseawholeseries
of them,each samplinga bit later than the previous one.In the design examplein
thisbookweuse16T&Hcircuits,followedby16sub-ADconverters.
ThetimingalignmentoftheseT&Hcircuitsneedstobeextremelyaccurate,and
conventionally,complextimingcalibrationisusedtoachievethis.Herehowever,it
isshownthatevenbetterperformancecanbeachievedbyacompactandgoodde-
signofthetimingcircuitwithoutrequiringanytimingcalibration.Thecircuitsusea
minimumoftransistorsthatcausetiminginaccuraciesandspeciallayouttechniques
arethefinishingtouch.Thankstotheabsenceofacontrolrangeforthetiming,the
amountofjitterisalsoreduced.
Tosavepowerandtokeeptheinputcapacitancelow,smallsizedtransistorsare
usedinthetime-interleavingT&Hcircuitry.OnlysimpleDCcalibrationsareneeded
to make the 16 paths behave equally over the whole input frequency range. An
extensiveanalysisofaccuracyandtimingrequirementsisgivenandcircuitsolutions
aredescribedindetail.
AftertheinputsignalissampledbyaT&Hsection,asub-ADCfinalizesthecon-
version.PipelineADconvertersarepopularforconversionratesaround100MS/s,
but they suffer from the fact that even in the first stage of the pipeline the full ac-
curacyforsettlingisrequired.Thismakesthedesignofhighspeedincombination
vii
viii Preface
with a high accuracy quite a challenge. Instead of that, we use sub-ADCs based
onSuccessiveApproximation(SA).Asexplainedinthisbook,thishasquitesome
advantages: A SAR ADC contains less critical analog blocks, and its power con-
sumptioncanbetentimeslessthanacomparablepipelineADC.
A potential disadvantage of Successive Approximation converters is the rela-
tively low maximum sample-rate. This problem is tackled with a new overrange
techniquethatgreatlyreducesthedemandsonsettlingtimeperconversionstepand
thatpostponesthecriticaldecisiontothelastconversionstep.Thisoffersgreatad-
vantage over a Pipeline ADC, where the first residue amplifier must settle to full
accuracytoavoidunrecoverableanalogerrorsintheconversionprocess.
Theworkdescribedinthisbookshowsstate-of-theartperformanceanddescribes
techniques, which gain popularity among today’s AD converter designers. We en-
joyedcarryingouttheresearchwithSimonandwehopeyouwillenjoyreadingthe
results.
UniversityofTwente,Enschede,TheNetherlands EdvanTuijl
BramNauta
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Analog-to-DigitalConversion . . . . . . . . . . . . . . . . . . . . 1
1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Time-interleavedTrackandHolds . . . . . . . . . . . . . . . . . . . 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 MismatchBetweenChannels . . . . . . . . . . . . . . . . . . . . 6
2.2.1 OriginofSpuriousTones . . . . . . . . . . . . . . . . . . 6
2.2.2 BandwidthMismatch . . . . . . . . . . . . . . . . . . . . 9
2.3 Time-interleavedTrackandHoldArchitectures. . . . . . . . . . . 12
2.3.1 ArchitectureWithoutaFrontendSampler . . . . . . . . . . 13
2.3.2 ArchitecturewithaFrontendSampler. . . . . . . . . . . . 17
2.3.3 ConclusionsonArchitectures . . . . . . . . . . . . . . . . 22
2.4 TrackandHoldBuffers . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 Even-orderDistortion . . . . . . . . . . . . . . . . . . . . 23
2.4.2 BufferDistortion . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 DistortionatHighFrequencieswithaCapacitiveLoad . . . 26
2.5 Bottom-plateSamplinginaTime-interleavedADC . . . . . . . . 28
2.6 NumberofChannels . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6.1 Sub-ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6.2 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.7.1 OffsetCalibration . . . . . . . . . . . . . . . . . . . . . . 34
2.7.2 GainCalibration . . . . . . . . . . . . . . . . . . . . . . . 34
2.7.3 TimingCalibration. . . . . . . . . . . . . . . . . . . . . . 34
2.7.4 BandwidthCalibration . . . . . . . . . . . . . . . . . . . . 35
2.8 JitterRequirementontheSample-clock . . . . . . . . . . . . . . . 35
2.9 SummaryandConclusions . . . . . . . . . . . . . . . . . . . . . 37
3 Sub-ADCArchitecturesforTime-interleavedADCs . . . . . . . . . 39
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ix
x Contents
3.2 TheSuccessiveApproximationADC . . . . . . . . . . . . . . . . 40
3.2.1 StandardSA-ADC . . . . . . . . . . . . . . . . . . . . . . 40
3.2.2 ArchitecturestoReducetheDACSettlingTime . . . . . . 41
3.2.3 OptimumNumberofConversionSteps . . . . . . . . . . . 49
3.2.4 Look-aheadLogic . . . . . . . . . . . . . . . . . . . . . . 53
3.2.5 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3 EfficiencyofSA-ADCVersusPipelineADC . . . . . . . . . . . . 57
3.3.1 SA-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.2 PipelineConverter . . . . . . . . . . . . . . . . . . . . . . 63
3.3.3 ComparisonandConclusionsonPowerEfficiency . . . . . 67
3.4 SummaryandConclusions . . . . . . . . . . . . . . . . . . . . . 68
4 ImplementationofaHigh-speedTime-interleavedADC . . . . . . . 71
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.2 ClockGeneration . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2.1 ClockBuffer . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.2.2 CMLClock-phaseGenerator . . . . . . . . . . . . . . . . 75
4.2.3 CMLtoCMOSConversionCircuit . . . . . . . . . . . . . 77
4.3 TrackandHold. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.1 BootstrappingoftheSample-switch. . . . . . . . . . . . . 78
4.3.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.3 Low-skewSwitch-driver . . . . . . . . . . . . . . . . . . . 85
4.3.4 ClockGenerationfortheT&H . . . . . . . . . . . . . . . 88
4.3.5 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4 Sub-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4.1 ChannelTiming . . . . . . . . . . . . . . . . . . . . . . . 93
4.4.2 SA-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.4.3 DACoftheSub-ADC . . . . . . . . . . . . . . . . . . . . 105
4.4.4 InterstageAmplifier . . . . . . . . . . . . . . . . . . . . . 108
4.4.5 Re-sampler . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.5.1 OffsetCalibration . . . . . . . . . . . . . . . . . . . . . . 114
4.5.2 GainCalibration . . . . . . . . . . . . . . . . . . . . . . . 114
4.6 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.7 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.7.1 MeasurementSetup . . . . . . . . . . . . . . . . . . . . . 117
4.7.2 MeasurementResults . . . . . . . . . . . . . . . . . . . . 119
4.8 ImprovedDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.8.1 MeasurementResultsoftheImprovedDesign . . . . . . . 122
4.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5 SummaryandConclusions . . . . . . . . . . . . . . . . . . . . . . . 125
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Contents xi
5.3 OriginalContributions . . . . . . . . . . . . . . . . . . . . . . . . 128
5.4 RecommendationsforFutureResearch . . . . . . . . . . . . . . . 129
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135