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Energy drives logic This “A” Wor(l)d, or 25 happy years in Newcastle and 100 Technical Reports on async.org.uk Alex Yakovlev uSystems Research Group Energy drives logic Newcastle University Outline • There is no Outline today!!! 22/07/2016 Asynchronous Workshop 2 How it all began … • Prior to that: – David Kinniment’s research on async processor designs and metastability and synchronsers in the 60s & 70s (Manchester) – My research on async design, models, interfaces in the 80s (St. Petersburg) – 1984-85 joint work (with Harry Whitfield, Albert Koelmans and Martin McLaughlin) on CAD for async (Newcastle) plus interactions with Brian Randell and Maciej Koutny on concurrency and dependability 22/07/2016 Asynchronous Workshop 3 Three main research threads Theory of Models and Tools concurrency algorithms Functionality Circuits Silicon Physics of Models and time, power Characterisations experiments and faults 22/07/2016 Asynchronous Workshop 4 The key element for success • Work of a team where all aspects of talent have a chance to develop and flourish • The team – both locally (Newcastle) and globally (worldwide) • Async research is a wonderful area which combines the three main threads and different people can exploit the three main categories of strengths: – Computer programming – Electronic (Circuits and Systems) design – Analytical 22/07/2016 Asynchronous Workshop 5 1990s: Logic Synthesis of Asynchronous Control • Formalisation of STGs and relation to state-based models; theory, models and tools for async controller synthesis, async processor prototyping • Projects: ASAP, ASTI, ACiD-WG • People: Jordi Cortadella, Luciano Lavagno, Alex Kondratyev, Mike Kishinevsky, Alexander Taubin, Albert Koelmans, Alexei Petrov, Alex Semenov, Enric Pastor, Lee Lloyd, Marta Pietkiewicz-Koutny • Some highlights: synthesis flow, monotonic cover, CSC solving, regions for async, Or-causality, relative-timing (‘lazy’ approach), unfolding-based verification (incl. nets with read-arcs), tool Petrify; application to Molnar’s counterflow pipeline design 22/07/2016 Asynchronous Workshop 6 Petrify flow D DSr+ DSw+ DTACK DTACK - LDS+ D+ LDS LDTACK+ LDS+ csc DSr D+ LDTACK - LDTACK+ synthesis LDTACK DTACK+ D- LDS - Logic asynchronous circuit DSr- DTACK+ (for Read Cycle) D- DSw- Read Cycle State Graph (VME bus) Boolean equations: csc + DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- LDS = D  csc DSr+ DTACK- DTACK = D LDTACK+ LDS- LDS- LDS- D = LDTACK DSr+ DTACK- csc = DSr D+ D- Complete State Coding (CSC) DTACK+ DSr- csc - 22/07/2016 Asynchronous Workshop 7 Example: counterflow pipeline Molnar’s 5-state TS: Solution: E Split a state (E) and insert PR PI a silent action (d), AR AI preserving behavioural I R AI AR (observational) equivalence F PI PR G C Example: counterflow pipeline E1 Molnar’s 5-state TS: d E E2 PR PI PR PI AR AI AR AI I I R R AI AR AI AR F F PI PR PI PR G G C C Example: counterflow pipeline E1 d Minimal set of regions: r1 = {E1,E2,I} <- pre(AR), post(PR) E2 PR PI r2 = {E1,E2,R} <- pre(AI), post (PI), co(d) AR AI r3 = {R,F,C} <- pre(PR), post(AR), co(G) I R r4 = {I,F,C} <- pre(PI), post(AI) AI AR r5 = {E2,I,C} <- pre(PI,AR), post(G,d) F r6 = {E2,R,C} <- pre(PR,AI), post(G,d) PI PR G r7 = {E1,I,F} <- pre(G,d), post(PR,AI) C Semi-elementary TS

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communication mechanisms. • Projects: HADES arbiters, ADC, Async communication mechanism . People: Johnson Fernandes, Mahdi.
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