Thermal-Structural Analyses of 3-D FPGAs Chunbo(Sam)Zhang,RamachandraKallam,AndrewDeceuster, AravindDasu,andLeijunLi MicronResearchCenter UtahStateUniversity April16,2009 MeasurementDeviceSetup MicronResearchCenter 2/13 FPGAConfiguration 1 XILINXSPARTANTQG140GQ0737madeinTaiwan. 2 InvestigatetheconfigurationofFPGAforareasonablemodelprototype. 3 IdentifytheconfigurationofFPGA,materialcomponents,and dimensions. MicronResearchCenter 3/13 FiniteElementModelofOneFPGA 1 Quartersymmetry 2 3-Dthermal-structuralcoupledmodel 3 Conductiveandconvectiveheattransfer 4 Simulationstopsafterthejunctiontemperaturesaturates(steady-state). MicronResearchCenter 4/13 3DTemperatureDistributionofOneFPGA 1 Asaturationphenomenonexistsinthetemperaturedistributionprofileof theFPGA. 2 Inthesteadystate,ahotzone,whoseshapeandvalueareindependentof time,isformed. 3 Theobservedtemperaturesaturationandsaturatedjunctiontemperature revealthethermalconditionoftheactiveFPGAlayer,whichisa valuablereferencetochipdesigners. MicronResearchCenter 5/13 3DThermalStressDistributionofOneFPGA 1 Thethermalstressconcentratesattheinterfacebetweencopperand epoxy+silverlayer,andepoxy+silverandsiliconlayers. 2 Themaximumstressislocatedatthegroove-shapedinterfaceofcopper andepoxypackage. 3 OntheFPGAlayer,thethermalstressconcentratesinthemiddleof edges,whichareparalleltothecoppergroovedirection. MicronResearchCenter 6/13 EffectsofFPGAParametersonJunctionTemperature 1 Themodelpredictedjunctiontemperatureisshowntolinearlyincrease withTR,RU,OBuffer,andFrequency. MicronResearchCenter 7/13 FiniteElementModelofTwoFPGAs 1 StackinganotherFPGAlayerontopoftheoriginalFPGAlayer. 2 In-betweentwoFPGAlayers,thesiliconlayerhasthesamethicknessas theFPGAlayers. MicronResearchCenter 8/13 3DTemperatureandStressDistributionsofTwoFPGAs 1 Forthetwo-layerFPGAs,thetemperatureandthermalstress distributionskeepthesameshapeasthoseoftheoneFPGA,buthave doubledvalues. MicronResearchCenter 9/13 ComparisonofTemperatureDistributionsonTwoFPGAs 1 Inthesteadystate,thetemperaturehasthesamedistributionandvalue onthetopFPGAlayer(left)andbottomFPGAlayer(right). MicronResearchCenter 10/13
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