Table Of Content

The Designer’s Guide to the Cortex-M Processor Family This pageintentionallyleftblank The Designer’s Guide to the Cortex-M Processor Family Third Edition Trevor Martin Hitex (UK) Ltd., Coventry, England, United Kingdom NewnesisanimprintofElsevier TheBoulevard,LangfordLane,Kidlington,OxfordOX51GB,UnitedKingdom 50HampshireStreet,5thFloor,Cambridge,MA02139,UnitedStates Copyright©2023ElsevierLtd.Allrightsreserved. Nopartofthispublicationmaybereproducedortransmittedinanyformorbyanymeans,electronicormechanical, includingphotocopying,recording,oranyinformationstorageandretrievalsystem,withoutpermissioninwritingfromthe publisher.Detailsonhowtoseekpermission,furtherinformationaboutthePublisher’spermissionspoliciesandour arrangementswithorganizationssuchastheCopyrightClearanceCenterandtheCopyrightLicensingAgency,canbefound atourwebsite:www.elsevier.com/permissions. ThisbookandtheindividualcontributionscontainedinitareprotectedundercopyrightbythePublisher(otherthanasmay benotedherein). Notices Knowledgeandbestpracticeinthisfieldareconstantlychanging.Asnewresearchandexperiencebroadenour understanding,changesinresearchmethods,professionalpractices,ormedicaltreatmentmaybecomenecessary. Practitionersandresearchersmustalwaysrelyontheirownexperienceandknowledgeinevaluatingandusingany information,methods,compounds,orexperimentsdescribedherein.Inusingsuchinformationormethodstheyshouldbe mindfuloftheirownsafetyandthesafetyofothers,includingpartiesforwhomtheyhaveaprofessionalresponsibility. Tothefullestextentofthelaw,neitherthePublishernortheauthors,contributors,oreditors,assumeanyliabilityforany injuryand/ordamagetopersonsorpropertyasamatterofproductsliability,negligenceorotherwise,orfromanyuseor operationofanymethods,products,instructions,orideascontainedinthematerialherein. ISBN:978-0-323-85494-8 ForInformationonallNewnespublications visitourwebsiteathttps://www.elsevier.com/books-and-journals Publisher:MaraE.Conner AcquisitionsEditor:TimPitts EditorialProjectManager:ZsereenaRoseMampusti ProductionProjectManager:ErragountaSaibabuRao CoverDesigner:ChristianJ.Bilbow TypesetbyMPSLimited,Chennai,India Contents About the author.................................................................................................xvii Foreword..............................................................................................................xix Preface.................................................................................................................xxi Acknowledgments...............................................................................................xxiii Chapter 1:Introduction to the Cortex-M Processor Family....................................... 1 Introduction....................................................................................................................1 Book Structure...............................................................................................................1 External URL.......................................................................................................1 Cortex-M Processor Family...........................................................................................2 Cortex Profiles.....................................................................................................2 Cortex-M Hardware Architectures.......................................................................3 Armv7-M.......................................................................................................................5 Cortex-M3............................................................................................................5 Cortex-M4............................................................................................................9 Cortex-M7..........................................................................................................12 Armv6-M.....................................................................................................................14 Cortex-M0..........................................................................................................14 Cortex-M01 .....................................................................................................17 Armv8-M.....................................................................................................................20 Cortex-M33/M23...............................................................................................20 Armv8.1-M..................................................................................................................22 Cortex-M55........................................................................................................22 Cortex-M85........................................................................................................23 Conclusion...................................................................................................................24 Chapter 2:Developing Software for the Cortex-M Family...................................... 25 Introduction..................................................................................................................25 v vi Contents Keil Microcontroller Development Kit.........................................................................25 Community Edition............................................................................................26 Software Packs...................................................................................................26 The Tutorial Exercises.................................................................................................27 Installation...................................................................................................................27 Exercise 2.1: Building a First Program........................................................................30 The Blinky Project.............................................................................................30 Configuring a Project from Scratch....................................................................32 Configuring the Run Time Environment............................................................33 Project Configuration.........................................................................................57 Exercise 2.2: Hardware Debug.....................................................................................69 How to Get Out of Jail Free...............................................................................75 Startup Barrier...................................................................................................75 Third-Party Configuration Tools..................................................................................75 Conclusion...................................................................................................................76 Chapter 3:Cortex-M Architecture........................................................................ 77 Introduction..................................................................................................................77 Cortex-M Instruction Set..............................................................................................77 Programmer’s Model and CPU Registers.....................................................................78 Program Status Register.....................................................................................80 Q Bit and Saturated Math’s Instructions............................................................81 Interrupts and Multicycle Instructions................................................................82 Conditional Execution—If Then blocks.............................................................82 Exercise 3.1: Saturated Maths and Conditional Execution.................................85 Cortex-M Memory Map and Busses.............................................................................91 Write Buffer.......................................................................................................93 Memory Barrier Instructions..............................................................................93 System Control Block........................................................................................94 Memory Access.................................................................................................94 Bit Manipulation..........................................................................................................95 Exercise 3.2: Bit Banding..................................................................................98 Dedicated Bit Manipulation Instructions............................................................99 SysTick Timer.............................................................................................................99 Nested Vector Interrupt Controller.............................................................................100 Operating Modes..............................................................................................101 Interrupt Handling—Entry...............................................................................101 Interrupt Handling—Exit.................................................................................103 Exiting Interrupt Routines Important!..............................................................104 Contents vii Exercise 3.3: SysTick Interrupt........................................................................104 Cortex-M Processor Exceptions.......................................................................109 Usage Fault......................................................................................................110 Bus Fault..........................................................................................................111 Memory Manager Fault....................................................................................111 Hard Fault........................................................................................................112 Enabling Fault Exceptions...............................................................................112 Priority and Preemption...................................................................................112 Groups and Subgroup.......................................................................................113 Processor Exceptions.......................................................................................114 Run Time Priority Control...............................................................................115 Exception Model..............................................................................................115 NVIC Tail Chaining.........................................................................................116 NVIC Late Arriving.........................................................................................116 NVIC POP Preemption....................................................................................117 Exercise 3.4: Working with Multiple Interrupts...............................................118 Bootloader Support..........................................................................................124 Exercise 3.5: Bootloader..................................................................................125 Power Management....................................................................................................130 Entering Low-Power Modes.............................................................................132 Configuring the Low-Power Modes.................................................................132 Exercise 3.6: Low-Power Modes......................................................................134 Moving From the Cortex-M3.....................................................................................135 Cortex-M4........................................................................................................136 Cortex-M0........................................................................................................136 Cortex-M01 ...................................................................................................138 Conclusion.................................................................................................................139 Chapter 4:Common Microcontroller Software Interface Standard.........................141 Introduction................................................................................................................141 CMSIS Specifications................................................................................................143 CMSIS-Core....................................................................................................145 CMSIS-RTOS..................................................................................................145 CMSIS-DSP.....................................................................................................145 CMSIS-Driver..................................................................................................145 CMSIS-SVD and DAP.....................................................................................146 CMSIS-Pack....................................................................................................147 CMSIS-NN......................................................................................................147 CMSIS-ZONE..................................................................................................148 viii Contents CMSIS-Build...................................................................................................148 Overview of CMSIS-Core..........................................................................................148 Coding Rules...................................................................................................148 CMSIS-Core Structure.....................................................................................152 Interrupts and Exceptions.................................................................................157 Exercise 4.1: CMSIS and User Code Comparison............................................160 CMSIS-Core Register Access..........................................................................161 CMSIS-Core CPU Intrinsic Instructions...........................................................163 Exercise 4.2: Intrinsic Bit Manipulation...........................................................164 CMSIS SIMD Intrinsics...................................................................................164 CMSIS-Core Debug Functions.........................................................................165 CMSIS Core Functions for Corex-M7..............................................................165 Armv8-M Support............................................................................................166 Conclusion.................................................................................................................166 Chapter 5:Advanced Architecture Features.........................................................167 Introduction................................................................................................................167 Cortex Processor Operating Modes............................................................................167 Exercise 5.1: Stack Configuration....................................................................170 Supervisor Call................................................................................................173 Exercise 5.2: SVC............................................................................................175 PEND_SV Exception.......................................................................................178 Exercise 5.3: Pend_SV.....................................................................................178 Interprocessor Events.................................................................................................181 Exclusive Access Instructions..........................................................................181 Exercise 5.4: Exclusive Access........................................................................184 Memory Protection Unit............................................................................................185 Configuring the MPU.......................................................................................187 CMSIS Core MPU Support..............................................................................190 Exercise 5.5: MPU Configuration....................................................................192 Memory Protection Unit Subregions................................................................198 Memory Protection Unit Limitations................................................................199 AHB Lite Bus Interface...................................................................................199 Conclusion.................................................................................................................201 Chapter 6:Cortex-M7 Processor.........................................................................203 Introduction................................................................................................................203 Superscaler Architecture............................................................................................205 Branch Prediction.......................................................................................................205 Contents ix Exercise 6.1: Simple Loop...............................................................................206 Bus Structure.............................................................................................................208 Memory Hierarchy.....................................................................................................210 Exercise 6.2: Locating Code and Data into the TCM.......................................211 Open Main.c..............................................................................................................213 Cache Units.....................................................................................................213 Cache Operation..............................................................................................214 Instruction Cache.............................................................................................217 Exercise 6.3: Instruction Cache........................................................................218 Data Cache.................................................................................................................218 Memory Barriers..............................................................................................220 Example 6.4: Data Cache.................................................................................220 MPU and Cache Configuration........................................................................221 Cache Policy....................................................................................................221 Double Precision Floating Point Unit.........................................................................228 Functional Safety.......................................................................................................228 Cortex-M7 Safety Features..............................................................................229 Safety Documentation......................................................................................229 Conclusion.................................................................................................................230 Chapter 7: Armv8-M Architecture and Processors................................................231 Introduction................................................................................................................231 Armv8-M...................................................................................................................231 Common Architectural Enhancements.............................................................232 Armv8 Baseline Enhancements........................................................................233 Armv8-M Mainline Enhancements...................................................................234 Coprocessor Interface.......................................................................................234 Trust Zone.......................................................................................................235 Exercise 7.1: TrustZone Configuration.............................................................242 Armv8.1-M................................................................................................................246 Helium Vector Extension.................................................................................247 CPU Extension.................................................................................................251 Exercise 7.2: Armv8.1 Performance.................................................................252 Coresight Debug Enhancements.......................................................................254 Memory Error Correction Codes......................................................................254 Performance Monitoring..................................................................................256 Security............................................................................................................257 CPU Comparison.......................................................................................................261 Conclusion.................................................................................................................261