Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test

138 Pages·2017·1.57 MB·English

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LSU Master's Theses Graduate School
2004
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Pavan K. Alli
Louisiana State University and Agricultural and Mechanical College
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Alli, Pavan K., "Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ
test methods" (2004). LSU Master's Theses. 1786.
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TESTING A CMOS OPERATIONAL AMPLIFIER CIRCUIT
USING A COMBINATION OF OSCILLATION AND I
DDQ
TEST METHODS

A Thesis

Submitted to the Graduate faculty of the
Louisiana State University and
Agricultural and Mechanical College
in partial fulfillment of the
requirements for the degree of
Master of Science in Electrical Engineering

In

The Department of Electrical and Computer Engineering

by
Pavan K Alli
Bachelor of Engineering, Osmania University, 2001
August 2004
ACKNOWLEDGEMENTS
I would like to dedicate my work to my parents, Mr. and Mrs. Alli Shankaraiah,
and my brother Kiran, for their constant prayers and encouragement throughout my life.
I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and
understanding throughout this work. His suggestions, discussions and constant
encouragement have helped me to get a deep insight in the field of VLSI design.
I would like to thank Dr. Theda Daniels Race and Dr. Pratul Ajmera for being a
part of my committee.
I am very thankful to Electrical Engineering and Biological Engineering
Departments, for supporting me financially during my stay at LSU.
I am very thankful to my friends Anand, Satish and Syam for their extensive help
throughout my graduate studies at LSU.
I take this opportunity to thank my friends Maruthi, Sudheer, Anoop and Siva for
their help and encouragement at times I needed them. I would also like to thank all my
friends here who made my stay at LSU an enjoyable and a memorable one.
Last of all I thank GOD for keeping me in good health and spirits throughout my
stay at LSU.

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TABLE OF CONTENTS
ACKNOWLEDGEMENTS..............................................................................................ii

LIST OF TABLES.............................................................................................................v

LIST OF FIGURES..........................................................................................................vi

ABSTRACT.......................................................................................................................x

CHAPTER 1. INTRODUCTION....................................................................................1
1.1 TESTING METHODOLOGY.........................................................................................6
1.2 ADVANTAGES OF COMBINED OSCILLATION AND IDDQ TESTING...............................8
1.3 CHAPTER ORGANIZATION........................................................................................9

CHAPTER 2. DESIGN FOR TEST OF A TWO-STAGE CMOS OPERATIONAL
AMPLIFIER USING OSCILLATION TESTING METHODOLOGY....................10
2.1 DESIGN OF A CMOS OPERATIONAL AMPLIFIER.....................................................10
2.1.1 A Two-Stage CMOS Amplifier Topology..................................................13
2.1.2 Current Mirrors............................................................................................15
2.1.3 Active Resistors...........................................................................................17
2.2 FREQUENCY ANALYSIS OF THE TWO-STAGE OP-AMP............................................29
2.3 STABILITY AND FEEDBACK ANALYSIS...................................................................31
2.4 TESTING FAULTS USING OSCILLATION TESTING METHODOLOGY..........................34
2.5 FAULT SENSITIVITY AND TOLERANCE BAND OF OSCILLATION FREQUENCY USING
MONTE-CARLO SIMULATION.................................................................................40

CHAPTER 3. I TESTING USING BUILT-IN CURRENT SENSOR ................44
DDQ
3.1 QUIESCENT CURRENT (IDDQ) TESTING IN CMOS CIRCUITS...................................44
3.2 PHYSICAL DEFECTS IN CMOS INTEGRATED CIRCUITS..........................................47
3.2.1 Bridging Faults.............................................................................................47
3.2.2 Open Faults..................................................................................................50
3.4 DEFINITION OF IDDQ OF A FAULTY CIRCUIT............................................................52
3.4.1 Description of I Testing for a Faulty Inverter........................................52
DDQ
3.5 DESIGN CONSIDERATIONS OF BICS.......................................................................54
3.5.1 Previously Proposed Schemes.....................................................................54
3.6 DESIGN AND IMPLEMENTATION OF THE BICS........................................................55
3.6.1 BICS in Normal Mode.................................................................................57
3.6.2 BICS in Test Mode......................................................................................58
3.7 BICS LAYOUT.......................................................................................................59
3.8 FAULT MODELS, SIMULATION AND DETECTION.....................................................59
3.8.1 Fault Injection Transistor.............................................................................61

CHAPTER 4. FAULT COVERAGE AND EXPERIMENTAL RESULTS FOR THE
COMBINED TEST PROCEDURE...............................................................................67
4.1 SIMULATED AMPLIFIER FUNCTIONAL TESTING RESULTS.......................................71
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4.2 SIMULATED IDDQ TESTING RESULTS......................................................................71
4.3 SIMULATED OSCILLATION TESTING RESULTS........................................................82
4.4 EXPERIMENTAL RESULTS.......................................................................................89

CHAPTER 5. CONCLUSION AND SCOPE OF FUTURE WORK.......................112

BIBLIOGRAPHY.........................................................................................................114

APPENDIX A: SPICE LEVEL 3 MOS MODEL PARAMETERS FOR
STANDARD N-WELL CMOS TECHNOLOGY [43]..............................................119

APPENDIX B: CHIP TESTABILITY........................................................................120

VITA...............................................................................................................................127

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LIST OF TABLES
Table.1: Theoretical I for testable faults.....................................................................81
DDQ
Table 2: Simulated frequency deviations under fault injections.......................................87
Table 3(a): Simulated fault coverage of oscillation testing..............................................88
Table 3(b): Simulated fault coverage of I testing........................................................88
DDQ
Table 4: Observed frequency deviations under fault injections......................................103
Table 5: Detected faults using theoretical and observed results for oscillation testing..104

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LIST OF FIGURES
Figure 1.1: An example to show how I can be used to detect physical defects............4
DDQ

Figure 1.2: Block diagram of the proposed test strategy....................................................7

Figure 2.1: Ideal operational amplifier.............................................................................11

Figure 2.2: Block diagram of an integrated operational amplifier....................................12

Figure 2.3: A two-stage CMOS operational amplifier......................................................14

Figure 2.4(a): p-MOS current mirror................................................................................16

Figure 2.4(b): n-MOS current mirror................................................................................16

Figure 2.5: Active resistors: (a) gate connected to drain and (b) gate connected to V . 19
DD

Figure 2.6: Layout of an operational amplifier design of the circuit of Fig 2.3...............22

Figure 2.7: Post layout transfer characteristics of the circuit of Fig 2.3...........................23

Figure 2.8: Post layout simulated response of the CMOS amplifier circuit of Fig 2.6....24

Figure 2.9: Post layout (Fig 2.6) simulated frequency response characteristics of the
amplifier circuit of Fig 2.3. Note: The open loop gain is 81dB and the 3dB
bandwidth is 1.1 kHz......................................................................................25

Figure 2.10: Post layout (Fig 2.6) simulated (a) amplitude and (b) phase versus frequency
response characteristics. Note: The phase margin is 770................................26

Figure 2.11: Post layout (Fig 2.6) simulated slew rate characteristics of the amplifier
circuit of Fig 2.3..............................................................................................27

Figure 2.12: Effect of pole-splitting capacitor on the gain and phase of an op-amp........28

Figure 2.13(a): A two-stage CMOS op-amp showing the feedback components............30

Figure 2.13(b): Two-port network equivalent small signal model of a two-stage op-amp
configuration of Fig. 2.13(a) with an equivalent zero nulling resistance (R ) 30
Z

Figure 2.14: Feedback circuit configuration.....................................................................32

Figure 2.15: Schematic representation of a testable op-amp [26]....................................35

Figure 2.16: A second order oscillator. (a) Block diagram (b) CMOS oscillator.............36
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Figure 2.17: Pole locations for the amplifier and oscillator configurations in s-domain. 39

Figure 2.18: Simulated natural oscillation frequency of the CUT oscillator....................41

Figure 2.19: Simulated FFT analysis for obtaining the natural oscillation frequency......42

Figure 2.20: Monte-Carlo analysis for parametric tolerances of important CUT
parameters. ......................................................................................................43

Figure 3.1: Block diagram of I testing.......................................................................46
DDQ

Figure 3.2: Drain-source, gate-source and inter-gate bridging faults in an inverter
chain................................................................................................................48

Figure 3.3: Bridging defects.............................................................................................49

Figure 3.4: Floating input and open FET – open circuit defects......................................51

Figure 3.5: Bridging fault causing I R drop and a path to the ground.......................53
DDQ B

Figure 3.6: CMOS built-in current sensor circuit with the CUT [33].............................56

Figure 3.7: Layout of a built-in current sensor circuit.....................................................60

Figure 3.8 (a): n-MOS Fault-injection transistor (FIT) used in the layout.......................63

Figure 3.8 (b): Fault-injection transistor between drain and source nodes of a CMOS
inverter............................................................................................................63

Figure 3.9: Layout of a two-stage CMOS amplifier with BICS showing the defects
induced in the CUT using fault-injection transistors.........…...…...…............65

Figure 3.10: Injected faults using FITs.............................................................................66

Figure 4.1(a): Circuit diagram of a two-stage CMOS amplifier with BICS with seven
fault-injection transistors................................................................................68

Figure 4.1(b): Layout of a two-stage CMOS amplifier with BICS with seven fault-
injection transistors.........................................................................................69

Figure 4.2: CMOS chip layout of a two-stage CMOS amplifier including BICS within a
padframe of 2.25mm × 2.25mm size..............................................................70

Figure 4.3: Microphotograph of the fabricated chip showing the CUT (CMOS amplifier)
and the BICS for I testing..........................................................................72
DDQ

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Figure 4.4: (a) Normal and (b) faulty output of the amplifier for a sinusoidal input voltage
of 100 mV p-p.................................................................................................73

Figure 4.5: Normal and faulty transfer characteristics of the amplifier............................74

Figure 4.6: Voltage gain versus frequency characteristics of the amplifier without faults
and with M5DSS fault....................................................................................75

Figure 4.7: Simulated BICS output of the circuit of Fig. 3.17 when Error-signal-1 for
defect-1 is activated........................................................................................77

Figure 4.8: Simulated BICS output of the circuit of Fig. 3.17 when Error-signal-3 for
defect-3 is activated........................................................................................78

Figure 4.9: Simulated BICS output with defects induced using fault injection
transistors........................................................................................................79

Figure 4.10: Influence of BICS on V .............................................................................80
SS

Figure 4.11: Output oscillation frequency for the injected faults (i) M10DSS (ii) M5GDS
(iii) M5DSS (iv) M11DSS (v) CCS (vi) M7GDS (vii) M6GDS....................83

Figure 4.12: Experimental ac-characteristics of the designed amplifier...........................91

Figure 4.13: Output response of the amplifier for an input sinusoidal p-p of 200 mV
applied across a voltage divider consisting of 1 kΩ and 100 kΩ at 5 kHz.....92

Figure 4.14: Step response of the amplifier to an input step of -2.5 to 2.5 V...................93

Figure 4.15: Experimental natural oscillation frequency..................................................94

Figure 4.16 (i): Experimental faulty (defect-1 M10DSS) oscillation frequency with V
E1
connected to V ............................................................................................95
DD

Figure 4.16 (ii): Experimental faulty (defect-2 M5GDS) oscillation frequency with V
E2
connected to 5V..............................................................................................96

Figure 4.16 (iii): Experimental faulty (defect-3 M5DSS) oscillation frequency with V
E3
connected to 5V..............................................................................................97

Figure 4.16 (iv): Experimental faulty (defect-4 M11DSS) oscillation frequency with V
E4
connected to 5V..............................................................................................98

Figure 4.16 (v): Experimental faulty (defect-5 CCS) oscillation frequency with V
E5
connected to 5V..............................................................................................99

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Figure 4.16 (vi): Experimental faulty (defect-6 M7GDS) oscillation frequency with V
E6
connected to 5V............................................................................................100
Figure 4.16 (vii): Experimental faulty (defect-7 M6DSS) oscillation frequency with V
E7
connected to 5V............................................................................................101

Figure 4.16 (viii): Experimental faulty (defect-8 M11G-VSS) oscillation frequency with
M11 gate connected to V ...........................................................................102
SS

Figure 4.17(i): BICS showing PASS/FAIL output from HP1660CS logic analyzer
corresponding to fault M10DSS. V and V are given a 1 kHz
ENABLE ERROR
signal.............................................................................................................105

Figure 4.17(ii): BICS showing PASS/FAIL output from HP1660CS logic analyzer
corresponding to fault M10DSS. V and V are given a 5 kHz
ENABLE ERROR
signal.............................................................................................................106

Figure 4.17(iii): BICS showing PASS/FAIL output from HP1600CS Logic Analyzer
corresponding to fault M10DSS. V connected to 400 Hz signal and
ENABLE
V is connected to 1 kHz.......................................................................107
ERROR

Figure 4.17(iv): BICS showing PASS/FAIL output from HP1660CS logic analyzer
corresponding to faults M10DSS and M5DSS. V is connected to GND
ENABLE
(BICS active) and Error-signals (V ) are given a 1 kHz signal........108
ERROR 1, 2

Figure 4.17(v): BICS showing PASS/FAIL output from HP1600CS Logic Analyzer
corresponding to fault M10DSS. V connected to 1 MHz signal and
ENABLE
V is connected to 1 kHz while V is being held at V ...........109
ERROR 1 ERROR 2 DD

Figure 4.17(vi): BICS showing PASS/FAIL output from HP1600CS Logic Analyzer
corresponding to fault M10DSS. V connected to 1 MHz signal and
ENABLE
V is connected to 1 kHz.......................................................................110
ERROR

Figure 4.17(vii): BICS showing PASS/FAIL output from HP1600CS Logic Analyzer
corresponding to fault M10DSS. V and V connected to 1 MHz
ENABLE ERROR
signal.............................................................................................................111

Figure 5.1: Block Diagram of the proposed BIST scheme.............................................113

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