STM32® 32-bit Flash microcontroller ARM® CortexTM-M3

80 Pages·2009·4.64 MB·English

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STM32 32-bit Flash
microcontroller
powered by
fi TM
ARM Cortex -M3
Technical part
10/10/2009
Silica Cortex
Speed Way
2009
Agenda
STM32 General Purpose (GP) technical presentation
STM32 architecture
STM32 system and standard peripherals
Advanced peripherals (High Density series)
STM32 Connectivity Line technical presentation
New peripherals: Ethernet, USB OTG, 2 x CAN
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STM32F103 Performance Line 16-512Kb Flash
(High Density series)
CORTEXTM-M3 F
2FS-cMhCannel 12-bit DAC 7C2 PMUHz ususMHz)MHz) Flash I/Flash I/F 2F2F5l5al6a6skskhBhB M M --e5e5m1m12o2okkrrByBy PPPPOoOowRwRRR/ee/PeePrgrgD D S1S1R.uR8.u8/Vp/PVpPpVpVlDylDy
ESTDMIO JJTTAAGG//SSWW DDeebbuugg Speed BSpeed Bmax 36/ 72max 36/ 72 3382824k4kBBBB B -B-a6a6c4c4kkkkuBuBp p S S DRDRaaAtAtaMaM XX3T32T2AKAKHLHLIz nIz on o+ t+st. s. 4 c R4c~Ri~1Cil1Cll6al6 aM tMtoHoHrzrzss
I1†2S channels DMA NNeesstteeddE Ev vTeTeMcMcttITIT C Cttrrll LiteHi-LiteHi-Arbiter (rbiter ( SSRRAAMM/ /N FNFOSOSRMRM/N/CNCAANNDD/C/CFF/ / 4o40o0sKsKcHcHPizPliz Lll+ Lal+aL tL8 t8oMoMrHrsHszz
23xxPAWDCMs timers 11 u xxp S Stoyy sD1st2Mtic iCcAkhk aT Tninmimeleserr fiARM fiARM Matrix / atrix / A LLCCCDCD lpo lpoacacrkrakal ll CelCelo loi ninnntttetrerrorfofalaclcee RRTTCC / / AAWWUU
M
Up to 112 I/Os (144 pins SDIO ARMfiPeripheral Bus
Bridge
Bridge
package) SD/SDIO/MMC/CE-ATA (max 36MHz)
1 x USB 2.0FS
1 x USB 2.0FS
Bridge
Bridge
2 x 16-bit PWM
SSyyn2nc chxhr or1on6nizi-zebedid tA APCC WT TimMime err us 66xx 1166--bbitit TTimimeerr 11 xx CCAANN 22..00BB
B
UUpp ttoo 1166 EExxtt.. ITITss ral z) 22 xx WWaattcchhddoogg 22 xx SSPPII// I†I†SS
e H (independent & window)
h M (independent & window)
UUpp ttoo 111122 I/IO/Oss erip x 72 22--cchhaannnneel l1 122--bbitit D DAACC 44S S xmxm UaUarStrSctcAaAarRrdRd T/ T/I /rI/LrDLDIaNIaN
P ma MMooddeemm C Coonntrtrooll
11 xx SSPPII fi (
M 33 x x1122--bbitit A ADDCC / /1 1MMssppss
11 xx UUSSAARRTT//LLININ AR uupp t oto 2 211 c chhaannnneelsls
Smartcard/IrDa
Smartcard/IrDa
MMooddeemm C Coonntrtrooll TTeemmppeerraattuurree SSeennssoorr 22 xx I2I2CC
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STM32 GP System Architecture
Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
BusMatrix added to Harvard architecture allows parallel access
Efficient DMA and Rapid data flow
Direct path to SRAM through arbiter, guarantees alternating access
Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
Increase Peripherals Speed for better performance
Dual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and
Low Speed APB (APB1) up to 36MHz
 Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz
toggling I/Os)
I-bus FF
//
II
h h FFLLAASSHH
D-bus ss
CCOORRTTEEXX--MM33 FlaFla
MMaasstteerr 11 BB
System
uu
ss SSRRAAMM
MM
SSllaavvee
aa
tt GGPPIIOOAA,,BB,,CC,,DD,,EE --AAFFIIOO (cid:150)(cid:150)
rixrix APB2 UUSSAARRTTT1T1I-I-MMSS1P1P I I--11EE -X-XATATIDIDCC11,,22 --
GGPP--DDMMAA AHB AAHHBB--AAPPBB22
MMaasstteerr 22 AAHHBB--AAPPBB11 APB1 UUSSAARRTT22,,33 --SSPPII22 --II22CC11,,22 (cid:150)(cid:150)
TTIIMM22,,33,,44 --IIWWDDGG(cid:150)(cid:150)WWWWDDGG (cid:150)(cid:150)
Arbiter Bridges UUSSBB (cid:150)(cid:150)CCAANN (cid:150)(cid:150)BBKKPP (cid:150)(cid:150)PPWWRR (cid:150)(cid:150)
Buses are not overloaded with data movement tasks
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STM32 GP standard
Both lines have
up to:
peripherals set
5 x USART
3 x SPI
2 x I2C
6 x 16-bit
Timers
RTC
The STM32 has a (cid:145)standard(cid:146) set of
Int 8 MHz RC
peripherals common to all versions of
Int 40 kHz RC
the family, offering unparalleled
2xWDG levels of flexibility for your
applications
POR/PDR/
PVD brown out
12 DMA
80% GPIO ratio
Up to 512KB
FLASH
Backup Domain
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Embedded FLASH
Both lines have
up to:
5 x USART
32K - 128K : 1K byte Page Size
3 x SPI
256K (cid:150) 512K : 2K Page Size
2 x I2C
10K write/erase cycles
6 x 16-bit
Timers Data Retention:
RTC
30 year lifetime over whole temperature range
Int 8 MHz RC
Information Block
Int 40 kHz RC
Big Information Block - 2K (cid:150) Bootloader
2xWDG
Small Information Block (cid:150) 512B (cid:150) User / Option Bytes
POR/PDR/
Protection
PVD brown out
Write Protection
12 DMA
Read Protection
80% GPIO ratio
Automatically triggers write protection on 1st 4K of
Up to 512KB
FLASH Flash
Backup Domain
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Flash Memory Accelerator
MMiissssiioonn:: Support 7722 MMHHzz operation directly from Flash memory
64-bits wide Flash with Prefetch (2 (cid:215) 64bits buffers)
Memory
Accelerator
s
Bit
16(cid:150)bitsmb-2
16 4 hu AARRBBIITTEERR ** FLASH
6T
(cid:150)
Instructions-BUS 32 (cid:133) MEMORY
s s s
16 bits 32 bits 16 bits bit bit bit
Thumb Thumb-2 Thumb-2 4 4 4
6 6 6
2
bitsmb-
2 u
3h
sT
t
CORTEX-M3 bi

4
CPU 62
bitsmb- ARRAY
2 u
3h
T
Data/Debug-BUS
16-bit 32 bits 8 bit
Data Data Data
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* The data (constant or literals ) are provided with the highest priority using the D-Bus.
Clock System
Both lines have
up to:
5 x USART
Multiple clock sources for full flexibility in RUN/Low Power
3 x SPI modes
2 x I2C HSE (High Speed External oscillator): 4MHz to 16MHz main osc which
can be multiplied by the PLL to provide a wide range of frequencies
6 x 16-bit
Timers
HSI (High Speed Internal RC): factory trimmed internal RC oscillator
RTC 8MHz +/- 1% over 0-70(cid:176)C temp range
Int 8 MHz RC PLL up to 64MHz
Int 40 kHz RC
Feeds System clock after reset or exit from STOP mode for fast startup
2xWDG startup time : 2us max
Clock Security System; Backup clock in case HSE osc fails
POR/PDR/
PVD brown out
LSI (Low Speed Internal RC): 40KHz internal RC for IWDG and optionally
for the RTC used for Auto Wake-Up (AWU) from STOP/STANDBY mode
12 DMA
Can be calibrated through Timer 5
80% GPIO ratio
LSE (Low Speed External oscillator): 32.768kHz osc provides a precise
Up to 512KB
time base with very low power consumption (max 1(cid:181)A). Optionally drives
FLASH
the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode
Backup Domain
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Clock Scheme
System Clock (SYSCLK) sources RTC Clock (RTCCLK) sources USB Clock (USBCLK) provided
from the internal PLL
 HSI  LSE
 HSE  LSI
Clock-out capability on the
 PLL  HSE clock divided by 128
MCO pin (PA.08) / max 50MHz
Configurable dividers provides Clock Security System (CSS) to backup clock in case of HSE
clock failure (HSI feeds the system clock)
AHB, APB1/2, ADC and TIM clocks
Enabled by SW w/ interrupt capability linked to Cortex NMI
HCLK
up to 72MHz
8MHz
HSI RC
PCLK1
up to 36MHz
/2
4M -H1z6 OOSSCC__OIUNT HSE Osc x2P..L.xL16 PLLCLK SuYpS tCoL 7K2 /P1r,eA2sH(cid:133)cBa5l 1e2r /P1r,A2esP,4cB,a81l,e 1r6 IEfl s(=eA1P)B 1 p xxre21s TIMxCLK
/2 MHz TIM2,3,4,
5,6,7
PCLK2
up to 72MHz
SYSCLK
HSI CSS APB2 If (APB2 pres
Prescaler =1) x1 TIM1CLK
MCO HSE /1,2,4,8,16 Else x2
TIM8CLK
PLLCLK
/2
/128
ADC
Prescaler ADCCLK
OSC32_IN 32.768KHz /2,4,6,8
LSE OSc RTCCLK
OSC32_OUT USB USBCLK
Prescaler 48MHz
/1,1.5
~40KHz
LSI RC IWDGCLK
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Power / Reset Management
Both lines have
up to:
5 x USART
POR / PDR (Power On Reset / Power Down Reset)
3 x SPI
Integrated POR / PDR circuitry guarantees proper product reset when
2 x I2C voltage is not in the product guaranteed voltage range (2V to 3.6V)
No need for external reset circuit
6 x 16-bit
Timers
POR and PDR have a typical hysteresis of 40mV
RTC
Int 8 MHz RC
Programmable Voltage Detector
Int 40 kHz RC
Enabled by software
2xWDG
Monitor the VDD power supply by comparing it to a threshold
POR/PDR/
Threshold configurable from 2.2V to 2.9V by step of 100mV
PVD brown out
Generate interrupt through EXTI Line16 (if enabled) when VDD <
12 DMA
Threshold and/or VDD > Threshold
80% GPIO ratio
 Can be used to generate a warning message and/or put the MCU into a safe
Up to 512KB state
FLASH
Backup Domain
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