Stand-Alone USB Transceiver Chip Silicon datasheet PDF
Preview Stand-Alone USB Transceiver Chip Silicon datasheet
Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 TUSB1210 Stand-Alone USB Transceiver Chip Silicon 1 Device Overview 1.1 Features 1 • USB2.0PHYTransceiverChip,Designedto SessionRequest Protocol(SRP) InterfaceWithaUSBControllerThroughaULPI • V OvervoltageProtectionCircuitryProtects BUS Interface, FullyCompliantWith: V PininRange–2Vto20V BUS – UniversalSerial BusSpecificationRev.2.0 • Internal5-VShort-CircuitProtectionofDP,DM, – On-The-GoSupplementtotheUSB2.0 andIDPinsfor CableShortingtoVBUSPin SpecificationRev.1.3 • ULPIInterface: – UTMI+LowPinInterface(ULPI)Specification – I/OInterface(1.8V)Optimizedfor Rev.1.1 Nonterminated50-Ω LineImpedance – ULPI12-pinSDRInterface – ULPICLOCKPin(60MHz)SupportsBoth Input • DP/DMLineExternalComponentCompensation andOutputClockConfigurations (Patent #US7965100B1) – FullyProgrammableULPI-Compliant Register • InterfacestoHost,PeripheralandOTGDevice Set Cores;OptimizedforPortableDevicesorSystem • FullIndustrialGradeOperatingTemperature ASICsWithBuilt-inUSBOTGDeviceCore RangeFrom–40°Cto85°C • CompleteUSBOTGPhysicalFront-EndThat • Availableina32-PinQuadFlatNoLead[QFN SupportsHostNegotiationProtocol(HNP)and (RHB)]Package 1.2 Applications • MobilePhones • VideoGameConsoles • PortableComputers • DesktopComputers • TabletDevices • PortableMusicPlayers 1.3 Description The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller through a ULPI interface. The device supports all USB2.0 data rates (high-speed 480 Mbps, full-speed 12 Mbps, and low- speed 1.5 Mbps), and is compliant to both host and peripheral modes. The device additionally supports a UART mode and legacy ULPI serial modes. TUSB1210 also supports the OTG (Ver1.3) optional addendumtotheUSB2.0Specification,includingHNPandSRP. The DP/DM external component compensation in the transmitter compensates for variations in the series impendenceinordertomatchwiththedatalineimpedanceandthereceiverinput impedance,to limitdata reflectionsandtherebyimproveeyediagrams. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) TUSB1210 VQFN(32) 5.00mmx5.00mm (1) Formoreinformation,seeSection8,MechanicalPackagingandOrderableInformation. 1 AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA. TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 www.ti.com 1.4 TUSB1210 Block Diagram POR VDDIO(32) VIO CTRL POR VBAT VBAT (21) BGAP POR ( 1)REFCLK 1V5 32K &REF DIG (11)CS (14)CFG RST_DIG (27)RESETB VDD15(12) ( 8)N/C USB-IP DIG (15)N/C VDD18(30) (16)N/C 1V8 PLL PHY PWR_ FSM (25)N/C VDD18(28) DIG (24)N/C VDD33(20) 3V3 + OTG PHY ULPI DP(18) OTG ANA + (17)CPEN DM(19) REGS TEST ID(23) VBUS(22) PKG Substrate (Ground) (26)C(29)S (31)D(2)NDATA(3:7,9 LOCKTP IRXT(7:0):10,13 ) 2 DeviceOverview Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 www.ti.com SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 Table of Contents 1 DeviceOverview......................................... 1 5 DetailedDescription................................... 15 .............................................. ............................................ 1.1 Features 1 5.1 Overview 15 ........................................... ........................... 1.2 Applications 1 5.2 FunctionalBlockDiagram 16 ............................................ ............................... 1.3 Description 1 5.3 ProcessorSubsystem 16 ........................... .............................................. 1.4 TUSB1210BlockDiagram 2 5.4 Memory 23 2 Revision History......................................... 3 6 Application,Implementation,andLayout......... 47 3 PinConfigurationandFunctions..................... 4 6.1 ApplicationInformation.............................. 47 ....................................... .................................. 3.1 PinDescription 4 6.2 TypicalApplication 47 4 Specifications ............................................ 6 6.3 PowerSupplyRecommendations................... 55 .......................... ............................................... 4.1 AbsoluteMaximumRatings 6 6.4 Layout 56 4.2 ESDRatings.......................................... 6 7 DeviceandDocumentationSupport............... 57 ................ ............................. 4.3 RecommendedOperatingConditions 6 7.1 DocumentationSupport 57 .................................. .......................................... 4.4 Thermal Information 6 7.2 Trademarks 57 .................................. ..................... 4.5 PowerConsumption 7 7.3 ElectrostaticDischargeCaution 57 ......................... ............................................. 4.6 I/OElectricalCharacteristics 8 7.4 Glossary 57 4.7 ClockSpecifications.................................. 9 8 MechanicalPackagingandOrderable ....................................... Information.............................................. 58 4.8 PowerModule 10 4.9 TimingParameterDefinitions ...................... 13 8.1 ViaChannel......................................... 58 4.10 InterfaceTargetFrequencies....................... 14 8.2 PackagingInformation .............................. 58 .............................. 4.11 Typical Characteristics 14 2 Revision History ChangesfromRevisionG(October2014)toRevisionH Page • MoveStorageTemperatureFrom:ESDRatingsTo:AbsoluteMaximumRatings .......................................... 6 • ChangedtheHandlingRatingstableTo:ESDRatings ......................................................................... 6 • AddedaMINvalueof1.2nsto"Outputdelay"inTable5-4 ................................................................. 18 • ChangedtheMAXvalueFrom:9nsTo:5nsin"Outputdelay"inTable5-4 .............................................. 18 ChangesfromRevisionF(July2013)toRevisionG Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................. 1 Copyright©2009–2015,TexasInstrumentsIncorporated RevisionHistory 3 SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 www.ti.com 3 Pin Configuration and Functions 3.1 Pin Description RHBPackage 32-PinOFN (TopView) B T K O 8 8 E C VDDI DIR VDD1 STP VDD1 RES CLO N/C 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 REFCLK 1 24 N/C NXT 2 23 ID DATA0 3 22 VBUS DATA1 4 21 VBAT DATA2 5 20 VDD33 DATA3 6 19 DM DATA4 7 GND 18 DP N/C 8 17 CPEN 9 0 1 2 3 4 5 6 1 1 1 1 1 1 1 5 6 S 5 7 G C C ATA ATA C DD1 ATA CF N/ N/ D D V D PinFunctions PIN A/D TYPE LEVEL DESCRIPTION NO. NAME V Referenceclockinput(square-waveonly).TietoGNDwhenpin26 DD33 (CLOCK)isrequiredtobeInputmode.Connecttosquare-wavereference 1 REFCLK A I 3.3V clockofamplitudeintherangeof3Vto3.6VwhenPin26(CLOCK)is requiredtobeOutputmode.Seepin14(CFG)descriptionforREFCLK inputfrequencysettings. 2 NXT D O V ULPINXToutputsignal DDIO 3 DATA0 D I/O V ULPIDATAinput/outputsignal0synchronizedtoCLOCK DDIO 4 DATA1 D I/O V ULPIDATAinput/outputsignal1synchronizedtoCLOCK DDIO 5 DATA2 D I/O V ULPIDATAinput/outputsignal2synchronizedtoCLOCK DDIO 6 DATA3 D I/O V ULPIDATAinput/outputsignal3synchronizedtoCLOCK DDIO 7 DATA4 D I/O V ULPIDATAinput/outputsignal4synchronizedtoCLOCK DDIO 8 N/C – – V Noconnect DDIO 9 DATA5 D I/O V ULPIDATAinput/outputsignal5synchronizedtoCLOCK DDIO 10 DATA6 D I/O V ULPIDATAinput/outputsignal6synchronizedtoCLOCK DDIO Active-highchipselectpin.WhenlowtheICisinpowerdownandULPI 11 CS D I V DDIO busistri-stated.Whenhighnormaloperation.TietoV ifunused. DDIO 12 VDD15 A power 1.5-VinternalLDOoutput.Connecttoexternalfilteringcapacitor. 13 DATA7 D I/O V ULPIDATAinput/outputsignal7synchronizedtoCLOCK DDIO REFCLKclockfrequencyconfigurationpin.Twofrequenciesare 14 CFG D I V DDIO supported:19.2MHzwhen0,or26MHzwhen1. 15 N/C – – – Noconnect 16 N/C – – – Noconnect 17 CPEN D O V CMOSactive-highdigitaloutputcontrolofexternal5VVBUSsupply DD33 18 DP A I/O V DPpinoftheUSBconnector DD33 4 PinConfigurationandFunctions Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 www.ti.com SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 PinFunctions (continued) PIN A/D TYPE LEVEL DESCRIPTION NO. NAME 19 DM A I/O V DMpinoftheUSBconnector DD33 20 V A power V 3.3-VinternalLDOoutput.Connecttoexternalfilteringcapacitor. DD33 DD33 21 V A power V Inputsupplyvoltageorbatterysource BAT BAT 22 V A power V V pinoftheUSBconnector BUS BUS BUS 23 ID A I/O V Identification(ID)pinoftheUSBconnector DD33 24 N/C – – – Noconnect 25 N/C – – – Noconnect ULPI60MHzclockonwhichULPIdataissynchronized. Twomodesarepossible: 26 CLOCK D O VDDIO InputMode:CLOCKdefaultsasaninput. Output Mode: When an input clock is detected on REFCLK pin (after 4 risingedges)thenCLOCKwillchangetoanoutput. Whenlow,alldigitallogic(except32kHzlogicrequiredforpowerup 27 RESETB D I V sequencing)includingregistersareresettotheirdefaultvalues,andULPI DDIO busistri-stated.Whenhigh,normalUSBoperation. 28 V A power V External1.8-Vsupplyinput.Connecttoexternalfilteringcapacitor. DD18 DD18 29 STP D I V ULPISTPinputsignal DDIO 30 V A power V External1.8-Vsupplyinput.Connecttoexternalfilteringcapacitor. DD18 DD18 31 DIR D O V ULPIDIRoutputsignal DDIO External1.8VsupplyinputfordigitalI/Os.Connecttoexternalfiltering 32 V A I V DDIO DDIO capacitor. Copyright©2009–2015,TexasInstrumentsIncorporated PinConfigurationandFunctions 5 SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 www.ti.com 4 Specifications 4.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Mainbatterysupplyvoltage(2) 0 5 V CC Wheresupplyrepresentsthevoltageapplied Voltageonanyinput(3) tothepowersupplypinassociatedwiththe –0.3 1×V +0.3 V CC input V input –2 20 V BUS ID,DP,DMinputs Stressconditionguaranteed24h –0.3 5.25 V V IOsupplyvoltage Continuous 1.98 V DDIO T Ambienttemperaturerange –40 85 °C A Absolutemaximumrating –40 150 T Ambienttemperaturerange °C J Forparametriccompliance –40 125 Ambienttemperatureforparametric Withmax125°Casjunctiontemperature –40 85 °C compliance DP,DMorIDpinsshortcircuitedtoV BUS DP,DM,IDhighvoltageshortcircuit supply,inanymodeofTUSB1210operation, 5.25 V continuouslyfor24hours DP,DMorIDpinsshortcircuitedtoGNDin DP,DM,IDlowvoltageshortcircuit anymodeofTUSB1210operation, 0 V continuouslyfor24hours T Storagetemperaturerange –55 125 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderSection4.3isnotimplied. Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theproductwillhavenegligiblereliabilityimpactifvoltagespikesof5.5Voccurforatotal(cumulativeoverlifetime)durationof5 milliseconds. (3) ExceptV input,V ,ID,DP,andDMpads BAT BUS 4.2 ESD Ratings VALUE UNIT Electrostaticdischarge(ESD) Humanbodymodel(HBM),perANSI/ESDA/JEDECJS001(1) ±2 V V (ESD) performance: Chargeddevicemodel(CDM),perJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Batterysupplyvoltage 2.7 3.6 4.8 V BAT VBAT BatterysupplyvoltageforUSB2.0compliancy WhenVDD33issuppliedinternally 3.15 V CERT (USB2.0certification) WhenV isshortedtoV externally 3.05 DD33 BAT V DigitalIOpinsupply 1.71 1.98 V DDIO T Ambienttemperaturerange –40 85 °C A 4.4 Thermal Information PARAMETER MEASUREMENTMETHOD VALUE UNIT θ Junction-to-ambientthermalresistance EIA/JESD51-1 34.72 °C/W JA θ top Junction-to-casetopthermalresistance(1) NocurrentJEDECspecification(2) 37.3 °C/W JC (1) TopissurfaceofthepackagefacingawayfromthePCB. (2) RefertomeasurementmethodinChapter2ofICPackageThermalMetrics(SPRA953). 6 Specifications Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 www.ti.com SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 Thermal Information (continued) PARAMETER MEASUREMENTMETHOD VALUE UNIT θ Junction-to-casebottomthermalresistance(3) NocurrentJEDECspecification(2) 3.6 °C/W JC bottom θ Junction-to-board thermalresistanceorjunction- EIA/JESD51-8. 10.3 °C/W JB to-pinthermalresistance Ψ Junction-to-topofpackage(notatruethermal EIA/JESD51-2 0.5 °C/W JT resistance) Ψ Junction-to-board(notatruethermalresistance) EIA/JESD51-6 10.5 °C/W JB (3) BottomsurfaceisthesurfaceofthepackagefacingtowardsthePCB. 4.5 Power Consumption Table4-1describesthepowerconsumptiondependingontheusecases. NOTE The typical power consumption is obtained in the nominal operating conditions and with the TUSB1210standalone. Table4-1.PowerConsumption TYPICAL MODE CONDITIONS SUPPLY UNIT CONSUMPTION I 8 VBAT OFFMode VBAT=3.6V,VDDIO=1.8V,VDD18 IVDDIO 3 µA =1.8V,CS=0V I 5 VDD18 I 16 TOTAL I 204 VBAT SuspendMode VBUS=5V,VBAT=3.6V,VDDIO= IVDDIO 3 µA 1.8V,Noclock I 3 VDD18 I 210 TOTAL I 24.6 VBAT HSUSBOperation VBAT=3.6V,VDDIO=1.8V,VDD18 IVDDIO 1.89 mA (SynchronousMode) =1.8V,activeUSBtransfer I 21.5 VDD18 I 48 TOTAL I 25.8 VBAT FSUSBOperation VBAT=3.6V,VDDIO=1.8V,active IVDDIO 1.81 mA (SynchronousMode) USBtransfer I 4.06 VDD18 I 31.7 TOTAL I 237 VBAT ResetMode RESETB=0V,VBUS=5V,VBAT IVDDIO 3 µA =3.6V,VDDIO=1.8V,Noclock IVDD18 3 I 243 TOTAL Copyright©2009–2015,TexasInstrumentsIncorporated Specifications 7 SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 www.ti.com 4.6 I/O Electrical Characteristics 4.6.1 Analog I/O Electrical Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT CPENOutputPin VOL CPENlow-leveloutputvoltage I =3mA 0.3 V CPEN OL VOH CPENhigh-leveloutputvoltage I =–3mA V –0.3 V CPEN OH DD33 4.6.2 Digital I/O Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CLOCK V Low-leveloutputvoltage 0.45 V OL V High-leveloutputvoltage Frequency=60MHz,Load=10pF V - V OH DDIO 0.45 STP,DIR,NXT,DATA0toDATA7 V Low-leveloutputvoltage 0.45 V OL V High-leveloutputvoltage Frequency=60MHz,Load=10pF V - V OH DDIO 0.45 4.6.3 Electrical Characteristics: Digital IO Pins (Non-ULPI) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT CS,CFG,RESETBInputPins V Maximumlow-levelinputvoltage 0.35*V V IL DDIO V Minimumhigh-levelinputvoltage 0.65*V V IH DDIO RESETBInputPinTimingSpec t Internalpower-onresetpulse w(POR) 0.2 μs width t AppliedtoexternalRESETBpin CLOCK w(RESET) ExternalRESETBpulsewidth 8 whenCLOCKistoggling. cycles 8 Specifications Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 www.ti.com SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 4.7 Clock Specifications 4.7.1 USB PLL Reference Clock TheUSBPLLblockgeneratestheclocksusedtosynchronize: • theULPIinterface(60MHzclock) • theUSB interface(dependingontheUSBdatarate, 480Mbps, 12Mbpsor1.5Mbps) TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block. Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK pin.BydefaultCLKpinisconfiguredasaninput. Twoclockconfigurationsarepossible: • Inputclockconfiguration(seeSection4.7.2) • Output clockconfiguration(seeSection4.7.3) 4.7.2 ULPI Input Clock Configuration InthismodeREFCLKmustbeexternallytiedtoGND. CLOCKremainsconfiguredasaninput. When the ULPI interface is used in input clock configuration, i.e., the 60 MHz ULPI clock is provided to TUSB1210onClockpin,thenthisisusedasthereferenceclockfor the480MHzUSBPLLblock. Table4-2.ElectricalCharacteristics:ClockInput PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Clockinputdutycycle 40 60% f Clocknominalfrequency 60 MHz CLK Clockinputrise/falltime In%ofclockperiodt (=1/f ) 10% CLK CLK Clockinputfrequencyaccuracy 250 ppm Clockinputintegratedjitter 600 psrms 4.7.3 ULPI Output Clock Configuration In this mode a reference clock must be externally provided on REFCLK pin When an input clock is detected on REFCLK pinthenCLKwillautomaticallychangetoanoutput,i.e.,60MHzULPIclockisoutputbyTUSB1210 on CLKpin. Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1210 via a configuration pin, CFG, see f in Table 6-2 for frequency correspondence. TUSB1210 supports REFCLK square-wave reference clock input only. Reference clock input must be square-wave of amplitude in the range 3.0Vto3.6V. Table4-3.ElectricalCharacteristics:REFCLK PARAMETER TESTCONDITIONS MIN TYP MAX UNIT REFCLKinputdutycycle 40 60% WhenCFGpinistiedtoGND 19.2 f REFCLKnominalfrequency MHz REFCLK WhenCFGpinistiedtoV 26 DDIO In%ofclockperiodt (= REFCLKinputrise/falltime REFCLK 20% 1/f ) REFCLK REFCLKinputfrequencyaccuracy 250 ppm REFCLKinputintegratedjitter 600 psrms REFCLKHIZLeakagecurrent 3 µA REFCLKHIZLeakagecurrent –3 Copyright©2009–2015,TexasInstrumentsIncorporated Specifications 9 SubmitDocumentationFeedback ProductFolderLinks:TUSB1210 TUSB1210 SLLSE09H–NOVEMBER2009–REVISEDJUNE2015 www.ti.com 4.7.4 Clock 32 kHz An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power clock to thesystem Table4-4. Performances PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Outputdutycycle Inputdutycycle40–60% 48% 50% 52% Outputfrequency 23 32 38 kHz 4.7.5 Reset AlllogicisresetifCS=0orV arenotpresent. BAT Alllogic(except32kHzlogic)isresetifV isnotpresent. DDIO PHYlogicisresetwhenanysuppliesarenotpresent(V ,V ,V ,V )orifRESETBpinislow. DDIO DD15 DD18 DD33 TUSB1210mayberesetmanuallybytogglingtheRESETBpintoGNDfor atlease200ns. IfmanualresetviaRESETBisnotrequiredthenRESETBpinmaybetiedtoV permanently. DDIO 4.8 Power Module This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of the suppliesdigitallycontrolledwithintheTUSB1210. 4.8.1 Power Modules 4.8.1.1 PowerProviders Table4-5.SummaryofTUSB1210Power Providers(1) TYPICAL MAXIMUM NAME USAGE TYPE VOLTAGE(V) CURRENT(mA) V Internal LDO 1.5 50 DD15 V External LDO 1.8 30 DD18 V Internal LDO 3.1 15 DD33 (1) V maybesuppliedexternally,orbyshortingtheV pintoV pinprovidedV minisin DD33 DD33 BAT BAT range[3.2V:3.6V].NotethattheV LDOwillalwayspower-onwhenthechipisenabled, DD33 irrespectiveofwhetherV issuppliedexternallyornot.InthecasetheV pinisnotsupplied DD33 DD33 externallyintheapplication,theelectricalspecsforthisLDOareprovidedbelow. 10 Specifications Copyright©2009–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:TUSB1210
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