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US 20030201508A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2003/0201508 A1 Yasukawa (43) Pub. Date: Oct. 30, 2003 (54) S01 SUBSTRATE, ELEMENT SUBSTRATE, (30) Foreign Application Priority Data SEMICONDUCTOR DEVICE, ELECTRO-OPTICAL APPARATUS, Nov. 30, 2000 (JP) .................................... .. 2000-365714 ELECTRONIC EQUIPMENT, METHOD OF Jun. 22, 2001 (JP) . . . . . . . . . . . . .. 2001-190521 MANUFACTURING THE S01 SUBSTRATE, Sep. 25, 2001 (JP) .................................... .. 2001-292645 METHOD OF MANUFACTURING THE ELEMENT SUBSTRATE, AND METHOD OF MANUFACTURING THE Publication Classi?cation ELECTRO-OPTICAL APPARATUs (51) Int. C1.7 .............................................. .. H01L 31/0232 (75) Inventor: Masahiro Yasukawa, Chino-shi (JP) (52) us. Cl. ............................................................ .. 257/435 Correspondence Address: OLIFF & BERRIDGE, PLC P. O. Box 19928 (57) ABSTRACT Alexandria, VA 22320 (US) (73) Assignee: Seiko Epson Corporation, Tokyo (JP) An SOI (Silicon On Insulator) substrate is provided With: a support substrate (201); a single crystal silicon layer (202) (21) Appl. No.: 10/431,401 disposed above one surface of the support substrate; an insulation portion (205) disposed betWeen the support sub (22) Filed: May 8, 2003 strate and the single crystal silicon layer, the insulation Related US. Application Data portion comprising a single layer of an insulation ?lrn or a larnination structure of a plurality of insulation ?lms, and (62) Division of application No. 09/988,332, ?led on Nov. including a silicon nitride ?lrn or a silicon nitride oxide ?lrn 19, 2001, noW Pat. No. 6,583,440. (204). 'M 202 j F/// ///////////// /////’ /////////////l203A %// :/// 204 205 \203B 201 Patent Application Publication Oct. 30, 2003 Sheet 1 0f 24 US 2003/0201508 A1 cm. I \.m. om vV @HE ////////////////?////////J////// ///////¢/////////////. . 0, 5 heet 2 0 S 2003/0201508 A1 FIG. 2 (b) WWW/Q5832 2038 \\\\\\\\\\\\\\\\\\&\\X\\\\\\\\\\\\\\\\\ FIG. 2 (C) 203B 204 205 203A 202A Patent Application Publication Oct. 30, 2003 Sheet 3 0f 24 US 2003/0201508 A1 FIG. 8 (8) 202A .206 ? ///J// / w FIG. 3 (b) 292A 7////////%//////%/////////// 203A . 204 205 ' 203B 201 200 ’ FIG. 3 (c) \ 202 201 Patent Application Publication Oct. 30, 2003 Sheet 5 0f 24 US 2003/0201508 A1 LmJ\W\\\\\\A\Q\\\\\\\\\\\\\\\\\\\\\\\\\\\\\.\\\M §_ m?ih FW%HEw‘ o,w N\30i7W/%/n%/? / _/ v. / . H/ |3_| NN..E 00. m. m %@OZNN/J/ . . mN@fr‘wwm. m x Patent Application Publication Oct. 30, 2003 Sheet 7 0f 24 US 2003/0201508 A1 FIG. 7 Patent Application Publication Oct. 30, 2003 Sheet 8 0f 24 US 2003/0201508 Al NFNE\\\\\\\\\\\..\\\\\\ N\\\\_~\\\M\ \ N\\\\ on, @8 iZ/ r $63,505 ZEED3F6ME5 @ \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\§\\\ \\\\§\\ x\\/K/M. $, 8 .2n.3 953:‘ /////////////////#/.///////////%w///////[//////?/f//////A///ww/9 /////A/X, // / // / oo////A, ww .w65 X<9\\\\4\\\\\\\\\\\ \ 1//////7Q/H////%//8/%/ g9Y cm .w...v.......i..__..t.........A.._..._..........,..._....... .................... ........... . \\\N\\ on Patent Application Publication Oct. 30, 2003 Sheet 9 0f 24 US 2003/0201508 A1 A A' 11 F1 G. 9( 8 ) I[ 11» f1 41/ 1'1 [Tu i 1 1 [71R1W/ A v 207 H F]: ii’ 7 A ‘K 1‘ i\}l2'\\ }m7 1 r7 _ G- 9(b) L H kmA a FIG. 9 (c) 1 L ' [I If ? Tiff Km_ 12 F]:G_ 9 [_—"__""' I 1 I 1 I 11a7 1 11 ~ 12 FIG, 9 (e) I? Z I 1 If a d/1OA FIG. FIG. 2 . 10A /1f la _ 1181f FIG- 9 Uzi! J4T i Y/Z JIYLI [I 1/ I21I _/1 1]\ ‘l 11a \mA FIG_ 9 2\ IFT/- Trg! 1fI 1L1 11/2/11r81 ! L11 1' 1 [C1 'ff1 f/l11f1f-f,f T if f“; _‘ \iOA

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strate and the single crystal silicon layer, the insulation portion comprising a single layer of an insulation ?lrn or a larnination structure of a plurality of
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