School of Innovation, Design and Engineering ABB AB Force Measurement MASTER THESIS IN ...

274 Pages·2009·12.37 MB·English

ABB AB Force Measurement
School of Innovation, Design and
Engineering
MASTER THESIS IN COMPUTER SCIENCE
High Performance FPGA-Based Computation and Simulation for MIMO
Measurement and Control Systems
November 2009
Author: JohanPalm
[email protected]
Examiner: Prof. LennartLindh
[email protected]
AcademicSupervisor: Prof. LennartLindh
[email protected]
IndustrialSupervisor: Dr. GeorgeFodor
[email protected]

Abstract
The Stressometer system is a measurement and control system used in cold rolling to im-
provetheflatnessofametalstrip. Inordertoachievethisgoalthesystememploysamultiple
input multiple output (MIMO) control system that has a considerable number of sensors and
actuators. As a consequence the computational load on the Stressometer control system be-
comes very high if too advance functions are used. Simultaneously advances in rolling mill
mechanical design makes it necessary to implement more complex functions in order for the
Stressometer system to stay competitive. Most industrial players in this market considers im-
provedcomputationalpower,formeasurement,controlandmodelingapplications,tobeakey
competitive factor. Accordingly there is a need to improve the computational power of the
Stressometersystem. Severaldifferentapproachestowardsthisobjectivehavebeenidentified,
e.g. exploitinghardwareparallelisminmoderngeneralpurposeandgraphicsprocessors.
Another approach is to implement different applications in FPGA-based hardware, either
tailored to a specific problem or as a part of hardware/software co-design. Through the use
of a hardware/software co-design approach the efficiency of the Stressometer system can be
increased, lowering overall demand for processing power since the available resources can
be exploited more fully. Hardware accelerated platforms can be used to increase the compu-
tational power of the Stressometer control system without the need for major changes in the
existinghardware. Thushardwareupgradescanbeassimpleasconnectingacabletoanaccel-
eratorplatformwhilehardware/softwareco-designisusedtofindasuitablehardware/software
partition,movingapplicationsbetweensoftwareandhardware.
Inordertodeterminewhetherthishardware/softwareco-designapproachisrealisticornot,
the feasibility of implementing simulator, computational and control applications in FPGA-
basedhardwareneedstobedetermined. Thisisaccomplishedbyselectingtwospecificappli-
cationsforacloserstudy,determiningthefeasibilityofimplementingaStressometermeasur-
ingrollsimulatorandaparallelCholeskyalgorithminFPGA-basedhardware.
Based on these studies this work has determined that the FPGA device technology is per-
fectly suitable for implementing both simulator and computational applications. The Stres-
someter measuring roll simulator was able to approximate the force and pulse signals of the
Stressometermeasuringrollatarelativemodestresourceconsumption,onlyconsuming1747
slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able
to provide performance in the range of GFLOP/s, exceeding the performance of the personal
computer used for comparison in several simulations, although at a very high resource con-
sumption. The result of this thesis, based on the two feasibility studies, indicates that it is
possible to increase the processing power of the Stressometercontrol system using the FPGA
devicetechnology.

Contents
I Background 1
1 Introduction 3
1.1 BackgroundandMotivation . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 ProblemFormulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Delimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 ChapterSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 DigitalSystemDesign 15
2.1 DeviceTechnologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 FieldProgrammableGateArrays(FPGAs) . . . . . . . . . . . . . . 18
2.2 HardwareDescriptiveLanguages(HDL) . . . . . . . . . . . . . . . . . . . . 25
2.2.1 Very High Speed Integrated Circuit Hardware Description Language
(VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.3 HigherLevelAbstraction . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 IPComponents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Hardware/SoftwareCo-Design . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5 SystemonaChip(SoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6.1 IBM’sCoreConnectBus . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 NetworkonaChip(NoC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 ArithmeticsinDigitalSystems 39
3.1 BinaryNumberSystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.1.1 ArithmeticsandFPGAs . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 VariableWordlengthandScaling . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 BinaryArithmetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
II The Stressometer System 45
4 TheStressometerMeasuringRoll 49
4.1 SlotandWrapAngles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
v
4.2 PressductorTechnology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 ForceSignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.1 ForceSignalMeasurement . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.2 ForceSignalvs. CarrierWave . . . . . . . . . . . . . . . . . . . . . 56
4.3.3 Discussion: ForceSignals . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 PulseSignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 ACaseStudyofPFSK187 61
5.1 PFSK187PowerSupply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2 HardwareResources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.1 XilinxVirtex-5FPGA . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2.2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.2.3 Flash: IntelStrataFlashP33,512Mbit . . . . . . . . . . . . . . . . . 62
5.2.4 FiberOpticInterface . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.5 CoaxialInterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.6 EthernetTransceiver(LAN8700i) . . . . . . . . . . . . . . . . . . . 63
5.2.7 DAandADConverters . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2.8 VoltageControlledCrystalOscillator(VCXO) . . . . . . . . . . . . 64
5.2.9 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.2.10 JTAG/Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.11 LightEmittingDiodes(LED) . . . . . . . . . . . . . . . . . . . . . 65
5.2.12 Pin-List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.13 AdditionalIOPorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2.14 PowerOnReset/Reset . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.15 ClockGeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2.16 PhaseRecovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 FPGAHardwareFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.2 ForceSignalsandCalibration . . . . . . . . . . . . . . . . . . . . . 73
5.3.3 ClockManagement . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.4 PI-RegulationofPFSA140 . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.5 SystemStatusandWarnings . . . . . . . . . . . . . . . . . . . . . . 75
5.3.6 LeakageLevel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3.7 Parameters,HardwareImagesandDiagnosticInformation . . . . . . 77
III The Stressometer Measuring Roll Simulator 79
6 Specification 83
6.1 Specification: MeasuringRollSimulator . . . . . . . . . . . . . . . . . . . . 83
6.2 Specification: PeripheralDevices . . . . . . . . . . . . . . . . . . . . . . . . 89
vi
7 PrototypeDesign 93
7.1 RollPosition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2 PulseSignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.3 CarrierWave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.4 SystemClockRe-synchronization . . . . . . . . . . . . . . . . . . . . . . . 102
7.5 ForceSignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.5.1 WordlengthandScaling . . . . . . . . . . . . . . . . . . . . . . . . 105
7.5.2 ForceSignalGenerationTimingRequirements . . . . . . . . . . . . 106
7.5.3 ForceGeneratorComponent . . . . . . . . . . . . . . . . . . . . . . 107
7.5.4 AmplitudeModulationComponent . . . . . . . . . . . . . . . . . . 109
7.5.5 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.5.6 ShiftRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.6 ForceSampleStorage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.7 DAController . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.8 ForceSignalModification . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.9 InternalVariables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.9.1 Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.9.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.9.3 ForceMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.9.4 ForceTransitionPointMemory . . . . . . . . . . . . . . . . . . . . 121
7.9.5 CarrierWaveLookupTable(ROM) . . . . . . . . . . . . . . . . . . 121
7.9.6 ValidInternalVariableValues . . . . . . . . . . . . . . . . . . . . . 121
7.9.7 InternalVariableUpdateSynchronization . . . . . . . . . . . . . . . 124
7.10 CommunicationsInterface . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.10.1 VariableMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.10.2 CommunicationRegisters . . . . . . . . . . . . . . . . . . . . . . . 126
7.10.3 ExternalCommunicationsSignals . . . . . . . . . . . . . . . . . . . 128
7.10.4 ServiceRequests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.10.5 InternalVariableUpdate . . . . . . . . . . . . . . . . . . . . . . . . 134
7.10.6 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.11 PeripheralDevices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.11.1 ClockGenerationandSynchronization . . . . . . . . . . . . . . . . 138
7.11.2 RollSimulatorController . . . . . . . . . . . . . . . . . . . . . . . 140
7.11.3 ConstantSignals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
8 ImplementationandVerification 143
8.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8.2 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
8.2.1 ForceSignalGenerationTiming . . . . . . . . . . . . . . . . . . . . 150
8.2.2 SignalGeneratorVerification . . . . . . . . . . . . . . . . . . . . . . 151
8.2.3 RollControllerandCommunicationsInterfaceVerification . . . . . . 156
8.2.4 VerificationofPeripheralDevices . . . . . . . . . . . . . . . . . . . 158
8.2.5 HardwareVerification . . . . . . . . . . . . . . . . . . . . . . . . . 158
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9 ConclusionsandFurtherWork 161
9.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
9.2 FurtherWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
IV Feasibility Study of Parallel FPGA-Based Cholesky Decomposi-
tion 167
10 LiteratureStudy 171
10.1 SerialCholeskyDecomposition . . . . . . . . . . . . . . . . . . . . . . . . 171
10.2 ParallelAlgorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10.2.1 ParallelPlatforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
10.2.2 ParallelAlgorithmDesign . . . . . . . . . . . . . . . . . . . . . . . 174
10.3 ScientificPapers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
10.3.1 CholeskyDecompositionusingFusedDatapathSynthesis . . . . . . 176
10.3.2 ImplementationofCholeskyLLT-DecompositionAlgorithminFPGA-
BasedRationalFractionParallelProcessor . . . . . . . . . . . . . . 178
10.3.3 Solving Systems of Linear Equations on the CELL Processor Using
CholeskyFactorization . . . . . . . . . . . . . . . . . . . . . . . . . 179
11 ParallelFPGA-basedCholeskyDecomposition 181
11.1 CholeskyAlgorithmDependenciesandInteractions . . . . . . . . . . . . . . 181
11.2 PrototypeDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
11.2.1 ArithmeticsUnit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.2.2 MemorySystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
11.2.3 ControlStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
11.2.4 FIFOComponents . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.3 PrototypeDesignSimulation . . . . . . . . . . . . . . . . . . . . . . . . . . 192
11.3.1 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
11.3.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
11.4 SuggestionsforaFinalImplementation . . . . . . . . . . . . . . . . . . . . 197
11.4.1 RevisedAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
11.4.2 MatrixInputControl . . . . . . . . . . . . . . . . . . . . . . . . . . 197
11.4.3 ClockFrequencyandLatency . . . . . . . . . . . . . . . . . . . . . 198
11.4.4 MemoryComponent . . . . . . . . . . . . . . . . . . . . . . . . . . 198
11.4.5 MemorySizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
11.4.6 ControlStructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
11.4.7 VariableMatrixSizes . . . . . . . . . . . . . . . . . . . . . . . . . . 199
11.4.8 ReducedArithmeticUnit . . . . . . . . . . . . . . . . . . . . . . . . 200
11.4.9 StructuralParallelArithmeticUnit . . . . . . . . . . . . . . . . . . . 203
12 ConclusionsandFurtherWork 205
12.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
12.2 FurtherWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
viii
V Conclusions and Further Work 209
13 Conclusions 211
14 FurtherWork 213
References 215
VI Appendixes 223
A PFSK187FPGAPinOut 224
B RollSimulator-InternalComponentsSignalInterfaces 235
B.1 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
B.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
B.3 Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
B.4 ShiftRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
C RollController-InstructionGeneration 251
D RollControl-InstructionVerification 257
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List of Figures
1.1 Hardware/SoftwareCo-Design . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 StressometerSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 ProgrammableLogicDevice . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 LookupTable(LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 LogicBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 ConfigurableLogicBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6 SystemonaChip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7 NetworkonaChip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1 BinaryFormat: Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2 BinaryFormat: FloatingPoint(SinglePrecision) . . . . . . . . . . . . . . . 40
3.3 BinaryFormat: FloatingPoint(DoublePrecision) . . . . . . . . . . . . . . . 40
3.4 BinaryFormat: FixedPoint . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 StressometerSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.6 FlatnessSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 TheStressometerMeasuringRoll . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 SeriallyConnectedSensorsinoneZone . . . . . . . . . . . . . . . . . . . . 50
4.3 WrapAngle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4 SlotandWrapAngle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 PressductorTransducer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6 SampledAmplitudeModulatedForceSignal . . . . . . . . . . . . . . . . . . 53
4.7 AmplitudeFrequencySpectraofSampledForceSignal . . . . . . . . . . . . 54
4.8 DemodulatedandFilteredForceSignal . . . . . . . . . . . . . . . . . . . . 55
4.9 MeanCenteredDemodulatedForceSignal . . . . . . . . . . . . . . . . . . . 56
4.10 Ratio: SlotAnglevs. WrapAngle . . . . . . . . . . . . . . . . . . . . . . . 57
4.11 Ratio: SlotAngleTimevs. CarrierWavePeriodTime . . . . . . . . . . . . . 57
4.12 Ratio: WrapAngleTimevs. CarrierWavePeriodTime . . . . . . . . . . . . 58
4.13 Pulse-Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.14 Sync-pulsevs. SlotAngle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1 PFSK187FPGABlockDiagram . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 ReceiverComponentBlockDiagram . . . . . . . . . . . . . . . . . . . . . . 70
x