Robust Sigma Delta Converters: And Their Application in Low-Power Highly-Digitized Flexible Receivers

306 Pages·2011·6.365 MB·Anglais

by  Arthur H.M. van Roermund

Robust Sigma Delta Converters
ANALOGCIRCUITSANDSIGNALPROCESSING
Consulting Editor: Mohammed Ismail. OhioStateUniversity
Forothertitlespublishedinthisseries,goto
www.springer.com/series/7381
Robert H.M. van Veldhoven (cid:2)
Arthur H.M. van Roermund
Robust
Sigma Delta
Converters
And Their Application in Low-Power
Highly-Digitized Flexible Receivers
Dr.ir.RobertH.M.vanVeldhoven Prof.dr.ir.ArthurH.M.vanRoermund
NXPSemiconductor,CentralR&D ElectricalEngineering
MixedSignalCircuits&Systems Mixed-signalMicroelectronicsGroup
HighTechCampus,Building32,room3.24 TechnicalUniversityEindhoven
5656AEEindhoven DenDolech2
TheNetherlands 5612AZEindhoven
[email protected] TheNetherlands
[email protected]
SeriesEditors:
MohammedIsmail MohamadSawan
205DreeseLaboratory ElectricalEngineeringDepartment
DepartmentofElectricalEngineering ÉcolePolytechniquedeMontréal
TheOhioStateUniversity Montréal,QC
2015NeilAvenue Canada
Columbus,OH43210
USA
ISBN978-94-007-0643-9 e-ISBN978-94-007-0644-6
DOI10.1007/978-94-007-0644-6
SpringerDordrechtHeidelbergLondonNewYork
LibraryofCongressControlNumber:2011920957
©SpringerScience+BusinessMediaB.V.2011
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Preface
ThefoundationofthisbookisbasedonmyveryexcitingtimeatPhilipsResearch
Laboratories and later at NXP Research. After 14 years of research on Sigma
Delta Converters and other IP blocks, I have learned that IC design and in par-
ticular the design of Sigma Delta Converters is not only a very interesting and
multi-dimensional research topic, but is also a religion interpreted differently by
eachandeveryindividual. Inthebook,Ihavetriedtoincludemywork,viewand
experience in the field of Sigma Delta Converters to give the reader a head-start
inthedesignofthisintriguingtypeofanalogtodigitalconverter.
Thebookrestsontheexperienceofdesigning,andcoachingotherstodesigntens
ofdifferentSigmaDeltaConvertersfornumerousapplications, likeinstrumenta-
tion,hearingaids,mobilephones,batterymanagement,carradio,etc. Inthisbook
the application area of Sigma Delta Converters is limited to cellular and connec-
tivityterminals,tolimitthescope.
I partitioned the book systematically, by looking at what exactly determines the
quality of a system. The found so-called quality indicators (Algorithmic accur-
acy, Robustness, Emission, Flexibility and Efficiency) are used as a framework
throughoutthebook. ThebookshowsalldifferentaspectsinthedesignofSigma
Delta Converters: system level specification and design, IP architecture, circuit
implementation and layout are all subjects of this book. Also the verification of
theory and silicon implementations by measurements is included. The book as-
sumessomebackgroundonreceiverarchitectures,SigmaDeltaConvertertheory,
andICdesign.
I very much hope you enjoy reading the book, and while reading, please do not
forget: Analogdesignisbeautiful,digitaldesignisjustatimediscreteandquan-
tizedportionofit.
Valkenswaard RobertH.M.vanVeldhoven
January2011
Contents
1 Introduction 1
1.1 Advanced,Multi-standardCellularandConnectivityTerminals
fortheMassMarket . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Complexity: MobilePhoneTrends,ItsImpactonthe
TransceiverandtheQuestforIntegration . . . . . . . . . . 3
1.1.2 TransistorScaling: VLSIandMoore . . . . . . . . . . . . 7
1.1.3 SmarterCircuits: Σ∆ModulatorsforMobileApplications . 9
1.2 BookAims . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 BookScope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 SystemQualityIndicators 13
2.1 TheSystemFunctionandItsIn-andOutputs . . . . . . . . . . . . 14
2.2 SystemQuality . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 RobustnesstoSecondaryInputs . . . . . . . . . . . . . . . 16
2.2.3 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.4 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.5 EmissionofSecondaryOutputs . . . . . . . . . . . . . . . 17
2.3 TheDigitalRevolution . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.1 TheAnalog-DigitalInterface . . . . . . . . . . . . . . . . 19
2.3.2 DigitalSystemsandtheQualityIndicators . . . . . . . . . 20
2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3 IntegratedReceiverArchitecturesforCellularandConnectivity 27
3.1 WirelessReceiverArchitecturesforDigitalCommunication . . . . 27
3.2 ReceiverArchitectureandtheQualityIndicators . . . . . . . . . . 30
3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
viii Contents
4 SpecificationsforA/DConvertersinCellularandConnectivity
Receivers 33
4.1 IFChoice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.1 ImageRejection . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.2 ZeroIFArchitecture . . . . . . . . . . . . . . . . . . . . . 35
4.1.3 NearZeroandHighIFArchitecture . . . . . . . . . . . . . 37
4.1.4 IFAssessment . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.5 DCOffsetand1/fNoise . . . . . . . . . . . . . . . . . . . 38
4.1.6 RFFront-EndandADC1/f-ThermalNoiseCorner
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Top-EndoftheADCDR . . . . . . . . . . . . . . . . . . . . . . 45
4.2.1 SignalLevels,Selectivity,andMaximumADCInputSignal 46
4.2.2 CrestFactor . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 ReceiverGain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3.1 Narrowvs. BroadBandAGC . . . . . . . . . . . . . . . . 50
4.4 Bottom-EndoftheADCDR . . . . . . . . . . . . . . . . . . . . 50
4.4.1 ReceiverSNRRequirement . . . . . . . . . . . . . . . . . 50
4.4.2 ReceiverNoiseFigureandADCNoiseFloor . . . . . . . . 51
4.5 DRoftheADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5.1 DRofaQuadratureADC . . . . . . . . . . . . . . . . . . 53
4.6 RFFront-EndandADCLinearityRequirements . . . . . . . . . . 54
4.6.1 SecondandThirdOrderHarmonicDistortion . . . . . . . . 54
4.6.2 SecondandThirdOrderIntermodulationandIP2andIP3 . 55
4.6.3 ThirdOrderCross-Modulation. . . . . . . . . . . . . . . . 58
4.6.4 DistortioninaQuadratureADC . . . . . . . . . . . . . . . 59
4.7 ExampleReceiverPartitioning: ReceiverforaGSMMobilePhone 61
4.7.1 IFChoiceandImageRejection . . . . . . . . . . . . . . . 62
4.7.2 Top-EndoftheADCDynamicRange . . . . . . . . . . . . 63
4.7.3 ReceiverSensitivityRequirementandtheBottom-End
oftheADCDynamicRange . . . . . . . . . . . . . . . . . 65
4.7.4 ReceiverLinearityRequirementandADCLinearity . . . . 66
4.8 ADCRequirements,theSystemQualityIndicatorsandΣ∆
ModulatorsastheADCArchitecture . . . . . . . . . . . . . . . . 67
4.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Σ∆ModulatorAlgorithmicAccuracy 71
5.1 Σ∆Modulatorswith1-bitQuantizerand1-bitDAC . . . . . . . . 73
5.2 Σ∆Modulatorswithb-bitQuantizerandb-bitDAC . . . . . . . . 78
5.3 Σ∆Modulatorswith1.5-bitQuantizerandDAC . . . . . . . . . . 79
5.4 Σ∆ModulatorswithMultipleQuantizersand1-bitDAC . . . . . 80
Contents ix
5.5 Σ∆ModulatorswithAdditiveError-FeedbackLoops . . . . . . . 82
5.6 CascadedΣ∆Modulators . . . . . . . . . . . . . . . . . . . . . . 87
5.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6 Σ∆ModulatorRobustness 91
6.1 Portable,TechnologyRobustAnalogIPandTime-to-Market . . . 92
6.1.1 TechnologyScalingandItsImpactonAnalogDesign
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.1.2 ADesignMethodologytoIncreasethePortability
ofAnalogIP . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2 ContinuousTimevs. DiscreteTimeLoopFilter . . . . . . . . . . 97
6.3 Feed-Forwardvs. FeedbackLoopFilter . . . . . . . . . . . . . . 99
6.4 GainAccuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.4.1 Σ∆Modulatorwith1-bitQuantizerand1-bitDAC . . . . . 101
6.4.2 Σ∆Modulatorwithb-bitQuantizerandb-bitDAC . . . . . 101
6.4.3 Σ∆ModulatorwithMultipleQuantizersand1-bitDAC . . 101
6.4.4 Σ∆ModulatorwithAdditiveErrorFeedbackLoops . . . . 102
6.4.5 CascadedΣ∆Modulators . . . . . . . . . . . . . . . . . . 104
6.5 CircuitNoiseoftheModulator’sInputStageandDAC . . . . . . . 105
6.5.1 RCIntegratorInputStageandSIFeedbackDAC . . . . . . 105
6.5.2 RCIntegratorInputStageandSRFeedbackDAC . . . . . 106
6.5.3 RCIntegratorInputStageandSCFeedbackDAC . . . . . 106
6.5.4 ImpactofSupplyVoltageontheCircuitNoise
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.6 Non-linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.6.1 Non-linearityintheInputStage . . . . . . . . . . . . . . . 108
6.6.2 Non-linearityintheQuantizerDecisionLevels . . . . . . . 111
6.6.3 Inter-Symbol-InterferenceintheFeedbackDAC . . . . . . 112
6.6.4 Non-linearityintheOutputLevelsoftheFeedbackDAC . . 113
6.7 AliasinginΣ∆Modulators . . . . . . . . . . . . . . . . . . . . . 116
6.7.1 AliasingintheQuantizer. . . . . . . . . . . . . . . . . . . 116
6.7.2 Σ∆ModulatorwithanSIFeedbackDAC . . . . . . . . . . 117
6.7.3 Σ∆ModulatorwithanSRFeedbackDAC . . . . . . . . . 120
6.7.4 Σ∆ModulatorwithanSCFeedbackDAC . . . . . . . . . 122
6.8 ExcessLoopDelay . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.8.1 ExcessTimeDelayCompensation . . . . . . . . . . . . . . 128
6.8.2 ExcessPhaseCompensation . . . . . . . . . . . . . . . . . 129
6.8.3 DACFeedbackPulseShapeandDelay . . . . . . . . . . . 131
6.9 ClockJitterinCTΣ∆Modulators . . . . . . . . . . . . . . . . . 132
6.9.1 TheTAJEModel . . . . . . . . . . . . . . . . . . . . . . . 133
x Contents
6.9.2 TheTPJEModel: SineWaveInducedJitter . . . . . . . . . 139
6.9.3 TheTPJEModel: SubstitutionofWhiteNoiseJitter
intheSineWaveInducedJitterModel. . . . . . . . . . . . 151
6.9.4 TheTPJEModel: SIVersusSCFeedbackDAC . . . . . . . 161
6.9.5 TheTPJEModel: AnApplicationDrivenChoiceBetween
SIVersusSCFeedbackDAC . . . . . . . . . . . . . . . . 162
6.10 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7 Σ∆ModulatorFlexibility 175
7.1 ReceiverDictatedFlexibilityRequirements . . . . . . . . . . . . . 175
7.2 Σ∆ModulatorClockFlexibility . . . . . . . . . . . . . . . . . . 177
7.2.1 ReceiverArchitecturewithLO-DependentADCClock . . . 178
7.2.2 ReceiverArchitecturewithaFlexibleandIndependentClock
fortheADC . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.2.3 ReceiverArchitecturewithFixed,IndependentADCClock 180
7.2.4 ChoiceofClockStrategy . . . . . . . . . . . . . . . . . . 182
7.3 InputStageandDACFlexibility . . . . . . . . . . . . . . . . . . 183
7.4 Loop-FilterFlexibility . . . . . . . . . . . . . . . . . . . . . . . . 183
7.5 QuantizerFlexibility . . . . . . . . . . . . . . . . . . . . . . . . . 185
7.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8 Σ∆ModulatorEfficiency 189
8.1 PowerEfficiencyFOM:FOM . . . . . . . . . . . . . . . . . . 191
DR
8.1.1 BenchmarkingwithFOM . . . . . . . . . . . . . . . . . 193
DR
8.2 PowerEfficiencyFOM:FOM . . . . . . . . . . . . . . . . . 194
eq,th
8.2.1 BenchmarkingwithFOM . . . . . . . . . . . . . . . . 197
eq,th
8.3 DistortionFOM:FOM . . . . . . . . . . . . . . . . . . . . 200
HD3D
8.3.1 BenchmarkingwithFOM . . . . . . . . . . . . . . . 202
HD3D
8.4 AreaFOM:FOM . . . . . . . . . . . . . . . . . . . . . . . . 205
area
8.4.1 BenchmarkingwithFOM . . . . . . . . . . . . . . . . 209
area
8.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
9 Σ∆ModulatorImplementationsandtheQualityIndicators 213
9.1 DigitizationatSystem/ApplicationLevel: Σ∆Modulators
forHighlyDigitizedReceivers . . . . . . . . . . . . . . . . . . . 214
9.1.1 A1.5-bitΣ∆ModulatorforUMTS . . . . . . . . . . . . . 215
9.1.2 ATriple-ModeΣ∆ModulatorforGSM-EDGE,CDMA2000
andUMTS . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9.1.3 AnExtremelyScalableΣ∆ModulatorforCellular
andWirelessApplications . . . . . . . . . . . . . . . . . . 232