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Real-Time Systems Design and Analysis PDF

530 Pages·2004·5.579 MB·English
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REAL-TIME SYSTEMS DESIGN AND ANALYSIS THIRD EDITION Phillip A. Laplante A JOHN WILEY & SONS, INC., PUBLICATION REAL-TIME SYSTEMS DESIGN AND ANALYSIS IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Stamatios V. Kartalopoulos, Editor in Chief M. Akay M. E. El-Hawary F. M. B. Periera J. B. Anderson R. Leonardi C. Singh R. J. Baker M. Montrose S. Tewksbury J. E. Brewer M. S. Newman G. Zobrist Kenneth Moore, Directorof Book and Information Services(BIS) Catherine Faduska, Senior Acquisitions Editor John Griffin, Acquisitions Editor Anthony VenGraitis, ProjectEditor REAL-TIME SYSTEMS DESIGN AND ANALYSIS THIRD EDITION Phillip A. Laplante A JOHN WILEY & SONS, INC., PUBLICATION TRADEMARKS (cid:1) 68000isaregisteredtrademarkofMotorola. (cid:1) 80386,80486areregisteredtrademarksofIntelCorporation. (cid:1) CICSisatrademarkofIBM. (cid:1) OS/2isatrademarkofIBM. (cid:1) PresentationManagerisatrademarkofIBM. (cid:1) SoftwareThroughPicturesisatrademarkofAonix. (cid:1) SpaceInvadersisatrademarkofTaito (cid:1) SPARCisatrademarkofSunMicrosystems. (cid:1) STATEMATEisatrademarkofi-Logix. (cid:1) UNIXisatrademarkofAT&T. (cid:1) VAXisatrademarkofDigitalEquipmentCorporation. Copyright2004bytheInstituteofElectricalandElectronicsEngineers,Inc.Allrightsreserved. PublishedsimultaneouslyinCanada. Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmittedinanyformorbyany means,electronic,mechanical,photocopying,recording,scanning,orotherwise,exceptaspermittedunder Section107or108ofthe1976UnitedStatesCopyrightAct,withouteitherthepriorwrittenpermissionofthe Publisher,orauthorizationthroughpaymentoftheappropriateper-copyfeetotheCopyrightClearanceCenter, Inc.,222RosewoodDrive,Danvers,MA01923,978-750-8400,fax978-750-4470,oronthewebat www.copyright.com.RequeststothePublisherforpermissionshouldbeaddressedtothePermissions Department,JohnWiley&Sons,Inc.,111RiverStreet,Hoboken,NJ07030,(201)748-6011,fax(201) 748-6008. LimitofLiability/DisclaimerofWarranty:Whilethepublisherandauthorhaveusedtheirbesteffortsin preparingthisbook,theymakenorepresentationsorwarrantieswithrespecttotheaccuracyorcompletenessof thecontentsofthisbookandspecificallydisclaimanyimpliedwarrantiesofmerchantabilityorfitnessfora particularpurpose.Nowarrantymaybecreatedorextendedbysalesrepresentativesorwrittensalesmaterials. Theadviceandstrategiescontainedhereinmaynotbesuitableforyoursituation.Youshouldconsultwitha professionalwhereappropriate.Neitherthepublishernorauthorshallbeliableforanylossofprofitoranyother commercialdamages,includingbutnotlimitedtospecial,incidental,consequential,orotherdamages. ForgeneralinformationonourotherproductsandservicespleasecontactourCustomerCareDepartmentwithin theU.S.at877-762-2974,outsidetheU.S.at317-572-3993orfax317-572-4002. Wileyalsopublishesitsbooksinavarietyofelectronicformats.Somecontentthatappearsinprint,however, maynotbeavailableinelectronicformat. LibraryofCongressCataloging-in-PublicationData: Laplante,PhillipA. Real-timesystemsdesignandanalysis:anengineer’shandbook/PhillipA.Laplante.–3rded. p. cm. Includesbibliographicalreferencesandindex. ISBN0-471-22855-9(cloth) 1.Real-timedataprocessing.2.Systemdesign.I.Title. QA76.54.L372004 004(cid:1).33–dc22 2003065702 PrintedintheUnitedStatesofAmerica. 10987654321 To my daughter, Charlotte CONTENTS PrefacetotheThirdEdition xvii 1 BasicReal-TimeConcepts 1 1.1 Terminology / 1 1.1.1 Systems Concepts / 2 1.1.2 Real-Time Definitions / 4 1.1.3 Events and Determinism / 7 1.1.4 CPU Utilization / 10 1.2 Real-Time System Design Issues / 12 1.3 Example Real-Time Systems / 13 1.4 Common Misconceptions / 15 1.5 Brief History / 16 1.5.1 Theoretical Advances / 17 1.5.2 Early Systems / 17 1.5.3 Hardware Developments / 18 1.5.4 Early Software / 18 1.5.5 Commercial Operating System Support / 19 1.6 Exercises / 20 2 HardwareConsiderations 23 2.1 Basic Architecture / 23 2.2 Hardware Interfacing / 24 2.2.1 Latching / 24 2.2.2 Edge versus Level Triggered / 25 2.2.3 Tristate Logic / 25 2.2.4 Wait States / 26 2.2.5 Systems Interfaces and Buses / 26 2.3 Central Processing Unit / 29 2.3.1 Fetch and Execute Cycle / 30 2.3.2 Microcontrollers / 30 vii

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