Quick Start Guide to VHDL

215 Pages·2019·18.598 MB·English

by  Brock J. LaMeres

Brock J. LaMeres
Quick Start
Guide to VHDL
Q S G VHDL
UICK TART UIDE TO
Q S G VHDL
UICK TART UIDE TO
1ST EDITION
Brock J. LaMeres
BrockJ.LaMeres
DepartmentofElectrical&ComputerEngineering
MontanaStateUniversity
Bozeman,MT,USA
ISBN978-3-030-04515-9 ISBN978-3-030-04516-6(eBook)
https://doi.org/10.1007/978-3-030-04516-6
LibraryofCongressControlNumber:2018963722
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Preface
The classical digital design approach (i.e., manual synthesis and minimization of logic) quickly
becomes impractical as systems become more complex. This is the motivation for the modern digital
designflow,whichuseshardwaredescriptionlanguages(HDL)andcomputer-aidedsynthesis/minimi-
zationtocreatethefinalcircuitry.ThepurposeofthisbookistoprovideaquickstartguidetotheVHDL
language,whichisoneofthetwomostcommonlanguagesusedtodescribelogicinthemoderndigital
design flow. This book is intended for anyone that has already learned the classical digital design
approach and is ready to begin learning HDL-based design. This book is also suitable for practicing
engineers that already know VHDL and need quick reference for syntax and examples of common
circuits. This book assumes that the reader already understands digital logic (i.e., binary numbers,
combinationalandsequentiallogicdesign,finitestatemachines,memory,andbinaryarithmeticbasics).
Since this book is designed to accommodate a designer that is new to VHDL, the language is
presentedinamannerthatbuildsfoundationalknowledgefirstbeforemovingintomorecomplextopics.
As such, Chaps. 1–5 only present functionality built into the VHDL standard package. Only after a
comprehensiveexplanationofthemostcommonlyusedpackagesfromtheIEEElibraryispresentedin
Chap. 7, are examples presented that use data types from the widely adopted STD_LOGIC_1164
package. For a reader that is using the book as a reference guide, it may be more practical to pull
examplesfromChaps.7–12astheyusethetypesstd_logicandstd_logic_vector. ForaVHDLnovice,
understandingthehistoryandfundamentalsoftheVHDLbasereleasewillhelpformacomprehensive
understanding of the language; thus it is recommended that the early chapters are covered in the
sequencetheyarewritten.
Bozeman,MT,USA BrockJ.LaMeres
v
Acknowledgments
ForAlexis.Theworldisabetterplacebecauseyouareinit.
vii
Contents
1:THEMODERNDIGITALDESIGNFLOW............................................................. 1
1.1 HISTORYOFHARDWAREDESCRIPTIONLANGUAGES..................................................... 1
1.2 HDLABSTRACTION................................................................................................ 4
1.3 THEMODERNDIGITALDESIGNFLOW........................................................................ 8
2:VHDLCONSTRUCTS.......................................................................................... 13
2.1 DATATYPES.......................................................................................................... 13
2.1.1 EnumeratedTypes...................................................................................... 13
2.1.2 RangeTypes............................................................................................... 14
2.1.3 PhysicalTypes............................................................................................ 14
2.1.4 VectorTypes................................................................................................ 14
2.1.5 User-DefinedEnumeratedTypes................................................................ 15
2.1.6 ArrayType................................................................................................... 15
2.1.7 Subtypes..................................................................................................... 15
2.2 VHDLMODELCONSTRUCTION................................................................................ 16
2.2.1 LibrariesandPackages.............................................................................. 16
2.2.2 TheEntity.................................................................................................... 17
2.2.3 TheArchitecture.......................................................................................... 17
3:MODELINGCONCURRENTFUNCTIONALITY.................................................. 21
3.1 VHDLOPERATORS................................................................................................ 21
3.1.1 AssignmentOperator.................................................................................. 21
3.1.2 LogicalOperators........................................................................................ 22
3.1.3 NumericalOperators................................................................................... 23
3.1.4 RelationalOperators................................................................................... 23
3.1.5 ShiftOperators............................................................................................ 23
3.1.6 ConcatenationOperator.............................................................................. 24
3.2 CONCURRENTSIGNALASSIGNMENTSWITHLOGICALOPERATORS................................... 24
3.2.1 LogicalOperatorExample:SOPCircuit..................................................... 25
3.2.2 LogicalOperatorExample:One-HotDecoder............................................ 26
3.2.3 LogicalOperatorExample:7-SegmentDisplayDecoder........................... 27
3.2.4 LogicalOperatorExample:One-HotEncoder............................................ 29
3.2.5 LogicalOperatorExample:Multiplexer....................................................... 31
3.2.6 LogicalOperatorExample:Demultiplexer.................................................. 32
3.3 CONDITIONALSIGNALASSIGNMENTS.......................................................................... 34
3.3.1 ConditionalSignalAssignmentExample:SOPCircuit............................... 34
3.3.2 ConditionalSignalAssignmentExample:One-HotDecoder..................... 35
3.3.3 ConditionalSignalAssignmentExample:7-SegmentDisplayDecoder.... 36
3.3.4 ConditionalSignalAssignmentExample:One-HotEncoder..................... 37
3.3.5 ConditionalSignalAssignmentExample:Multiplexer................................ 38
3.3.6 ConditionalSignalAssignmentExample:Demultiplexer........................... 39
ix
x (cid:129) Contents
3.4 SELECTEDSIGNALASSIGNMENTS............................................................................. 41
3.4.1 SelectedSignalAssignmentExample:SOPCircuit................................... 41
3.4.2 SelectedSignalAssignmentExample:One-HotDecoder......................... 42
3.4.3 SelectedSignalAssignmentExample:7-SegmentDisplayDecoder........ 43
3.4.4 SelectedSignalAssignmentExample:One-HotEncoder......................... 44
3.4.5 SelectedSignalAssignmentExample:Multiplexer.................................... 45
3.4.6 SelectedSignalAssignmentExample:Demultiplexer............................... 46
3.5 DELAYEDSIGNALASSIGNMENTS............................................................................... 48
3.5.1 InertialDelay............................................................................................... 48
3.5.2 TransportDelay........................................................................................... 48
4:STRUCTURALDESIGNANDHIERARCHY........................................................ 53
4.1 COMPONENTS........................................................................................................ 53
4.1.1 ComponentInstantiation............................................................................. 53
4.1.2 PortMapping............................................................................................... 53
4.2 STRUCTURALDESIGNEXAMPLES:RIPPLECARRYADDER............................................. 56
4.2.1 HalfAdders.................................................................................................. 56
4.2.2 FullAdders.................................................................................................. 56
4.2.3 RippleCarryAdder(RCA).......................................................................... 58
4.2.4 StructuralModelofaRippleCarryAdderinVHDL.................................... 59
5:MODELINGSEQUENTIALFUNCTIONALITY..................................................... 65
5.1 THEPROCESS....................................................................................................... 65
5.1.1 SensitivityLists............................................................................................ 65
5.1.2 WaitStatements.......................................................................................... 66
5.1.3 SequentialSignalAssignments.................................................................. 67
5.1.4 Variables...................................................................................................... 68
5.2 CONDITIONALPROGRAMMINGCONSTRUCTS................................................................ 70
5.2.1 If/ThenStatements...................................................................................... 70
5.2.2 CaseStatements......................................................................................... 71
5.2.3 InfiniteLoops............................................................................................... 73
5.2.4 WhileLoops................................................................................................. 75
5.2.5 ForLoops.................................................................................................... 75
5.3 SIGNALATTRIBUTES................................................................................................ 76
6:PACKAGES.......................................................................................................... 81
6.1 STD_LOGIC_1164............................................................................................. 81
6.1.1 STD_LOGIC_1164ResolutionFunction..................................................... 82
6.1.2 STD_LOGIC_1164LogicalOperators........................................................ 83
6.1.3 STD_LOGIC_1164EdgeDetectionFunctions........................................... 83
6.1.4 STD_LOGIC_1164TypeConverstionFunctions........................................ 84
6.2 NUMERIC_STD................................................................................................. 85
6.2.1 NUMERIC_STDArithmeticFunctions........................................................ 85
6.2.2 NUMERIC_STDLogicalFunctions............................................................. 87
6.2.3 NUMERIC_STDComparisonFunctions..................................................... 87
6.2.4 NUMERIC_STDEdgeDetectionFunctions............................................... 87
Contents (cid:129) xi
6.2.5 NUMERIC_STDConversionFunctions...................................................... 88
6.2.6 NUMERIC_STDTypeCasting.................................................................... 88
6.3 TEXTIOANDSTD_LOGIC_TEXTIO................................................................... 89
6.4 OTHERCOMMONPACKAGES.................................................................................... 92
6.4.1 NUMERIC_STD_UNSIGNED..................................................................... 92
6.4.2 NUMERIC_BIT............................................................................................ 92
6.4.3 NUMERIC_BIT_UNSIGNED...................................................................... 93
6.4.4 MATH_REAL............................................................................................... 93
6.4.5 MATH_COMPLEX....................................................................................... 95
6.4.6 LegacyPackages(STD_LOGIC_ARITH/UNSIGNED/SIGNED)............... 95
7:TESTBENCHES.................................................................................................. 99
7.1 TESTBENCHOVERVIEW.......................................................................................... 99
7.2 GENERATINGSTIMULUSVECTORSUSINGFORLOOPS................................................. 101
7.3 AUTOMATEDCHECKINGUSINGREPORTANDASSERTSTATEMENTS................................ 102
7.3.1 ReportStatement........................................................................................ 102
7.3.2 AssertStatement......................................................................................... 103
7.4 USINGEXTERNALI/OINTESTBENCHES................................................................... 104
7.4.1 WritingtoanExternalFilefromaTestBench............................................ 104
7.4.2 WritingtoSTD_OUTPUTfromaTestBench............................................. 107
7.4.3 ReadingfromanExternalFileinaTestBench.......................................... 109
7.4.4 ReadingSpace-DelimitedDatafromanExternalFileinaTestBench..... 111
8:MODELINGSEQUENTIALSTORAGEANDREGISTERS................................. 117
8.1 MODELINGSCALARSTORAGEDEVICES..................................................................... 117
8.1.1 D-Latch........................................................................................................ 117
8.1.2 D-Flip-Flop................................................................................................... 118
8.1.3 D-Flip-FlopwithAsynchronousResets...................................................... 118
8.1.4 D-Flip-FlopwithAsynchronousResetandPreset...................................... 119
8.1.5 D-Flip-FlopwithSynchronousEnable........................................................ 120
8.2 MODELINGREGISTERS............................................................................................ 121
8.2.1 RegisterswithEnables............................................................................... 121
8.2.2 ShiftRegisters............................................................................................. 122
8.2.3 RegistersasAgentsonaDataBus............................................................ 123
9:MODELINGFINITESTATEMACHINES.............................................................. 127
9.1 THEFSMDESIGNPROCESSANDAPUSH-BUTTONWINDOWCONTROLLEREXAMPLE...... 127
9.1.1 ModelingtheStateswithUser-Defined,EnumeratedDataTypes............. 128
9.1.2 TheStateMemoryProcess........................................................................ 129
9.1.3 TheNextStateLogicProcess.................................................................... 129
9.1.4 TheOutputLogicProcess.......................................................................... 130
9.1.5 ExplicitlyDefiningStateCodeswithSubtypes........................................... 132
9.2 FSMDESIGNEXAMPLES........................................................................................ 133
9.2.1 SerialBitSequenceDetectorinVHDL....................................................... 133
9.2.2 VendingMachineControllerinVHDL......................................................... 135
9.2.3 2-Bit,BinaryUp/DownCounterinVHDL.................................................... 137
xii (cid:129) Contents
10:MODELINGCOUNTERS.................................................................................... 143
10.1MODELINGCOUNTERSWITHASINGLEPROCESS......................................................... 143
10.1.1CountersinVHDLUsingtheTypeUNSIGNED......................................... 143
10.1.2CountersinVHDLUsingtheTypeINTEGER............................................ 144
10.1.3CountersinVHDLUsingtheTypeSTD_LOGIC_VECTOR...................... 145
10.2COUNTERSWITHENABLESANDLOADS...................................................................... 148
10.2.1ModelingCounterswithEnables................................................................ 148
10.2.2ModelingCounterswithLoads................................................................... 149
11:MODELINGMEMORY........................................................................................ 153
11.1MEMORYARCHITECTUREANDTERMINOLOGY.............................................................. 153
11.1.1MemoryMapModel..................................................................................... 153
11.1.2Volatilevs.NonvolatileMemory.................................................................. 154
11.1.3Read-Onlyvs.Read/WriteMemory............................................................ 154
11.1.4RandomAccessvs.SequentialAccess..................................................... 154
11.2MODELINGREAD-ONLYMEMORY.............................................................................. 155
11.3MODELINGREAD/WRITEMEMORY............................................................................ 158
12:COMPUTERSYSTEMDESIGN......................................................................... 163
12.1COMPUTERHARDWARE........................................................................................... 163
12.1.1ProgramMemory........................................................................................ 164
12.1.2DataMemory............................................................................................... 164
12.1.3Input/OutputPorts....................................................................................... 164
12.1.4CentralProcessingUnit.............................................................................. 164
12.1.5AMemory-MappedSystem........................................................................ 166
12.2COMPUTERSOFTWARE............................................................................................ 168
12.2.1OpcodesandOperands.............................................................................. 169
12.2.2AddressingModes...................................................................................... 169
12.2.3ClassesofInstructions................................................................................ 170
12.3COMPUTERIMPLEMENTATION:AN8-BITCOMPUTEREXAMPLE...................................... 177
12.3.1Top-LevelBlockDiagram............................................................................ 177
12.3.2InstructionSetDesign................................................................................. 178
12.3.3MemorySystemImplementation................................................................ 179
12.3.4CPUImplementation................................................................................... 184
APPENDIXA:LISTOFWORKEDEXAMPLES...................................................... 207
INDEX....................................................................................................................... 211