Principles of secure processor architecture design PDF
Preview Principles of secure processor architecture design
Series ISSN: 1935-3235 S Z E Synthesis Lectures on F E R Computer Architecture Series Editor: Margaret Martonosi,Princeton University P R I Principles of N Principles of Secure Processor Architecture Design C I P Jakub Szefer, Yale University L E S O Secure Processor With growing interest in computer security and the protection of the code and data which execute on F S commodity computers, the amount of hardware security features in today’s processors has increased E C significantly over the recent years. No longer of just academic interest, security features inside processors U R have been embraced by industry as well, with a number of commercial secure processor architectures E available today. This book gives readers insights into the principles behind the design of academic and P Architecture Design R commercial secure processor architectures. Secure processor architecture research is concerned with O C exploring and designing hardware features inside computer processors, features which can help protect E S confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor S O architecture research that focuses on performance, efficiency, and energy as the first-order design R objectives, secure processor architecture design has security as the first-order design objective (while still A R keeping the others as important design aspects that need to be considered). C H This book presents the different challenges of secure processor architecture design to graduate I T students interested in research on architecture and hardware security and computer architects working E C in industry interested in adding security features to their designs. It educates readers about how the T U different challenges have been solved in the past and what are the best practices, i.e., the principles, for R E design of new secure processor architectures. Based on the careful review of past work by many computer D architects and security researchers, readers also will come to know the five basic principles needed for E S secure processor architecture design.The book also presents existing research challenges and potential IG new research directions. Finally, it presents numerous design suggestions,as well as discussing pitfalls N Jakub Szefer and fallacies that designers should avoid. About SYNTHESIS This volume is a printed version of a work that appears in the Synthesis M Digital Library of Engineering and Computer Science. Synthesis O books provide concise, original presentations of important research and R G development topics, published quickly, in digital and print formats. A N & Synthesis Lectures on C L A Computer Architecture Y store.morganclaypool.com P O O L Principles of Secure Processor Architecture Design Synthesis Lectures on Computer Architecture Editor MargaretMartonosi,PrincetonUniversity FoundingEditorEmeritus MarkD.Hill,UniversityofWisconsin,Madison SynthesisLecturesonComputerArchitecturepublishes50-to100-pagepublicationsontopics pertainingtothescienceandartofdesigning,analyzing,selectingandinterconnectinghardware componentstocreatecomputersthatmeetfunctional,performanceandcostgoals.Thescopewill largelyfollowthepurviewofpremiercomputerarchitectureconferences,suchasISCA,HPCA, MICRO,andASPLOS. PrinciplesofSecureProcessorArchitectureDesign JakubSzefer 2018 General-PurposeGraphicsProcessorArchitectures TorM.Aamodt,WilsonWaiLunFung,andTimothyG.Rogers 2018 CompilingAlgorithmsforHeterogenousSystems StevenBell,JingPu,JamesHegarty,andMarkHorowitz 2018 ArchitecturalandOperatingSystemSupportforVirtualMemory AbhishekBhattacharjeeandDanielLustig 2017 DeepLearningforComputerArchitects BrandonReagen,RobertAdolf,PaulWhatmough,Gu-YeonWei,andDavidBrooks 2017 On-ChipNetworks,SecondEdition NatalieEnrightJerger,TusharKrishna,andLi-ShiuanPeh 2017 iv Space-TimeComputingwithTemporalNeuralNetworks JamesE.Smith 2017 HardwareandSoftwareSupportforVirtualization EdouardBugnion,JasonNieh,andDanTsafrir 2017 DatacenterDesignandManagement:AComputerArchitect’sPerspective BenjaminC.Lee 2016 APrimeronCompressionintheMemoryHierarchy SomayehSardashti,AngelosArelakis,PerStenström,andDavidA.Wood 2015 ResearchInfrastructuresforHardwareAccelerators YakunSophiaShaoandDavidBrooks 2015 AnalyzingAnalytics RajeshBordawekar,BobBlainey,andRuchirPuri 2015 CustomizableComputing Yu-TingChen,JasonCong,MichaelGill,GlennReinman,andBingjunXiao 2015 Die-stackingArchitecture YuanXieandJishenZhao 2015 Single-InstructionMultiple-DataExecution ChristopherJ.Hughes 2015 Power-EfficientComputerArchitectures:RecentAdvances MagnusSjälander,MargaretMartonosi,andStefanosKaxiras 2014 FPGA-AcceleratedSimulationofComputerSystems HariAngepat,DerekChiou,EricS.Chung,andJamesC.Hoe 2014 v APrimeronHardwarePrefetching BabakFalsafiandThomasF.Wenisch 2014 On-ChipPhotonicInterconnects:AComputerArchitect’sPerspective ChristopherJ.Nitta,MatthewK.Farrens,andVenkateshAkella 2013 OptimizationandMathematicalModelinginComputerArchitecture TonyNowatzki,MichaelFerris,KarthikeyanSankaralingam,CristianEstan,NilayVaish,and DavidWood 2013 SecurityBasicsforComputerArchitects RubyB.Lee 2013 TheDatacenterasaComputer:AnIntroductiontotheDesignofWarehouse-Scale Machines,SecondEdition LuizAndréBarroso,JimmyClidaras,andUrsHölzle 2013 Shared-MemorySynchronization MichaelL.Scott 2013 ResilientArchitectureDesignforVoltageVariation VijayJanapaReddiandMeetaSharmaGupta 2013 MultithreadingArchitecture MarioNemirovskyandDeanM.Tullsen 2013 PerformanceAnalysisandTuningforGeneralPurposeGraphicsProcessingUnits (GPGPU) HyesoonKim,RichardVuduc,SaraBaghsorkhi,JeeChoi,andWen-meiHwu 2012 AutomaticParallelization:AnOverviewofFundamentalCompilerTechniques SamuelP.Midkiff 2012 PhaseChangeMemory:FromDevicestoSystems MoinuddinK.Qureshi,SudhanvaGurumurthi,andBipinRajendran 2011 vi Multi-CoreCacheHierarchies RajeevBalasubramonian,NormanP.Jouppi,andNaveenMuralimanohar 2011 APrimeronMemoryConsistencyandCacheCoherence DanielJ.Sorin,MarkD.Hill,andDavidA.Wood 2011 DynamicBinaryModification:Tools,Techniques,andApplications KimHazelwood 2011 QuantumComputingforComputerArchitects,SecondEdition TzvetanS.Metodi,ArvinI.Faruque,andFredericT.Chong 2011 HighPerformanceDatacenterNetworks:Architectures,Algorithms,andOpportunities DennisAbtsandJohnKim 2011 ProcessorMicroarchitecture:AnImplementationPerspective AntonioGonzález,FernandoLatorre,andGrigoriosMagklis 2010 TransactionalMemory,SecondEdition TimHarris,JamesLarus,andRaviRajwar 2010 ComputerArchitecturePerformanceEvaluationMethods LievenEeckhout 2010 IntroductiontoReconfigurableSupercomputing MarcoLanzagorta,StephenBique,andRobertRosenberg 2009 On-ChipNetworks NatalieEnrightJergerandLi-ShiuanPeh 2009 TheMemorySystem:YouCan’tAvoidIt,YouCan’tIgnoreIt,YouCan’tFakeIt BruceJacob 2009 vii FaultTolerantComputerArchitecture DanielJ.Sorin 2009 TheDatacenterasaComputer:AnIntroductiontotheDesignofWarehouse-Scale Machines LuizAndréBarrosoandUrsHölzle 2009 ComputerArchitectureTechniquesforPower-Efficiency StefanosKaxirasandMargaretMartonosi 2008 ChipMultiprocessorArchitecture:TechniquestoImproveThroughputandLatency KunleOlukotun,LanceHammond,andJamesLaudon 2007 TransactionalMemory JamesR.LarusandRaviRajwar 2006 QuantumComputingforComputerArchitects TzvetanS.MetodiandFredericT.Chong 2006 Copyright©2019byMorgan&Claypool Allrightsreserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmittedin anyformorbyanymeans—electronic,mechanical,photocopy,recording,oranyotherexceptforbriefquotations inprintedreviews,withoutthepriorpermissionofthepublisher. PrinciplesofSecureProcessorArchitectureDesign JakubSzefer www.morganclaypool.com ISBN:9781681730011 paperback ISBN:9781681730028 ebook ISBN:9781681734040 hardcover DOI10.2200/S00864ED1V01Y201807CAC045 APublicationintheMorgan&ClaypoolPublishersseries SYNTHESISLECTURESONCOMPUTERARCHITECTURE Lecture#45 SeriesEditor:MargaretMartonosi,PrincetonUniversity FoundingEditorEmeritus:MarkD.Hill,UniversityofWisconsin,Madison SeriesISSN Print1935-3235 Electronic1935-3243
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