Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems

124 Pages·2015·5.13 MB·English

by  Yu Lin

ACSP · Analog Circuits And Signal Processing
Yu Lin
Hans Hegt
Kostas Doris
Arthur H.M. van Roermund
Power-Efficient
High-Speed
Parallel-Sampling ADCs
for Broadband
Multi-carrier Systems
Analog Circuits and Signal Processing
Series editors
Mohammed Ismail, Dublin, USA
Mohamad Sawan, Montreal, Canada
More information about this series at http://www.springer.com/series/7381
Yu Lin Hans Hegt Kostas Doris
(cid:129) (cid:129)
Arthur H.M. van Roermund
fi
Power-Ef cient High-Speed
Parallel-Sampling ADCs
for Broadband Multi-carrier
Systems
123
YuLin KostasDoris
NXPSemiconductors NXPSemiconductors
Eindhoven Eindhoven
TheNetherlands TheNetherlands
Hans Hegt ArthurH.M. vanRoermund
Department ofElectrical Engineering Department ofElectrical Engineering
Eindhoven University of Technology Eindhoven University of Technology
Eindhoven Eindhoven
TheNetherlands TheNetherlands
ISSN 1872-082X ISSN 2197-1854 (electronic)
Analog CircuitsandSignal Processing
ISBN978-3-319-17679-6 ISBN978-3-319-17680-2 (eBook)
DOI 10.1007/978-3-319-17680-2
LibraryofCongressControlNumber:2015937536
SpringerChamHeidelbergNewYorkDordrechtLondon
©SpringerInternationalPublishingSwitzerland2015
Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpart
of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations,
recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission
orinformationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar
methodologynowknownorhereafterdeveloped.
The use of general descriptive names, registered names, trademarks, service marks, etc. in this
publicationdoesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfrom
therelevantprotectivelawsandregulationsandthereforefreeforgeneraluse.
The publisher, the authors and the editors are safe to assume that the advice and information in this
book are believed to be true and accurate at the date of publication. Neither the publisher nor the
authorsortheeditorsgiveawarranty,expressorimplied,withrespecttothematerialcontainedhereinor
foranyerrorsoromissionsthatmayhavebeenmade.
Printedonacid-freepaper
SpringerInternationalPublishingAGSwitzerlandispartofSpringerScience+BusinessMedia
(www.springer.com)
Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Book Aim and Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Enhancing ADC Performance by Exploiting Signal
Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Introduction to Analog-to-Digital Converters . . . . . . . . . . . . . . . 5
2.2 ADC Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Conversion Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4 ADC Figure-of-Merit . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 ADC Performance Limitations and Trends. . . . . . . . . . . . . . . . . 11
2.4 ADC Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Exploiting Signal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Parallel-Sampling ADC Architecture for Multi-carrier
Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Introduction to Multi-carrier Transmission. . . . . . . . . . . . . . . . . 23
3.2 Statistical Amplitude Properties of Multi-carrier Signals . . . . . . . 25
3.3 ADC Requirements for Multi-carrier Signals . . . . . . . . . . . . . . . 28
3.4 Power Reduction Techniques for Thermal-Noise
Limited ADCs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5 A Parallel-Sampling ADC Architecture. . . . . . . . . . . . . . . . . . . 36
3.5.1 Principle of the Parallel-Sampling ADC Architecture . . . . 37
3.5.2 Advantages of the Parallel-Sampling Architecture. . . . . . . 39
3.5.3 Impact of Mismatch Between Signal Paths . . . . . . . . . . . 43
v
vi Contents
3.6 Implementation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.7 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Implementations of the Parallel-Sampling ADC Architecture . . . . . 51
4.1 Parallel-Sampling Architecture Applied to a Pipeline ADC . . . . . 52
4.1.1 Pipeline ADCs Architecture. . . . . . . . . . . . . . . . . . . . . . 52
4.1.2 A Parallel-Sampling First Stage for a Pipeline ADC. . . . . 53
4.1.3 Implementation and Operation of the First Stage . . . . . . . 56
4.1.4 Simulation and Comparison. . . . . . . . . . . . . . . . . . . . . . 60
4.2 Parallel-Sampling Architecture Applied to a TI SAR ADC . . . . . 64
4.2.1 A Hierarchical TI-SAR ADC Architecture. . . . . . . . . . . . 64
4.2.2 A Parallel-Sampling Frontend Stage
for a TI-SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 Implementation and Operation. . . . . . . . . . . . . . . . . . . . 67
4.2.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3 Design of a 1 GS/s 11-b Parallel-Sampling ADC
for Broadband Multi-Carrier Systems . . . . . . . . . . . . . . . . . . . . 73
4.3.1 Architecture and Operation Overview. . . . . . . . . . . . . . . 74
4.3.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.3.3 Layout and Test-Chip Implementation. . . . . . . . . . . . . . . 83
4.3.4 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.3.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.3.6 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3.7 Comparison with State-of-the-Art. . . . . . . . . . . . . . . . . . 95
4.4 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5 Conclusions and Recommendations. . . . . . . . . . . . . . . . . . . . . . . . 103
5.1 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2 Recommendations for Future Research . . . . . . . . . . . . . . . . . . . 104
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Appendix: A Dynamic Latched Comparator for Low Supply
Voltage Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Symbols and Abbreviations
A Scaling factor
ADC Analog-to-digital converter
ADE Cadence analog design environment
ADSL Asymmetric digital subscriber line
AMP Amplifier
AWG Arbitrary waveform generator
BER Bit error rate
C Capacitance (F)
CICC IEEE Custom Integrated Circuits Conference
CMOS Complementary metal oxide semiconductor
CR Clipping ratio
CS Current source
CS-DAC Current steering digital-to-analog converter
D Auxiliary path data output
aux
D Digital data output
out
D(n) Digital data symbol
DAC Digtial-to-analog converter
DFT Discrete Fourier transform
DNL Differential non-linearity (LSB)
DOCSIS Data over cable service interface specification
DUT Device under test
E{∙} Expectation
ECG Electrocardiography
ENOB Effective number of bits (bit)
ERBW Effective resolution bandwidth (Hz)
ESSCIRC IEEE European Solid State Circuits Conference
f(x) Probability density function
F(x) Distribution function
f Carrier frequency
c
f Subcarrier spacing
cs
FE Front end
vii
viii SymbolsandAbbreviations
FFT Fast Fourier transform
FinFET Fin-shaped field-effect transistor
FOM Figure of merit
FS Full scale amplitude measured by a single sinusoid (V)
f Sampling rate (Hz)
s
g(t) Pulse function
GSM Global system for mobile communications
GS/s Gigahertz sample per second
HD Harmonic distortion
HVQFN Heatsink very-thin quad flat-pack no-leads
I/O Input/output
I2C Inter-integrated circuit
IC Integrated circuit
IEEE Institute of Electrical and Electronics Engineers
IFFT Inverse fast Fourier transform
IMD Inter-modulation distortion
INL Integral nonlinearity (LSB)
ISSCC IEEE international Solid-State Circuits Conference
k Boltzmann’s constant (Joules/Kelvin)
L Clipping level of an ADC (V)
clip
LSB Least significant bit
LTE Long-Term Evolution
MC-CDMA Multi-carrier code division multiple access
MDAC Multiplying digital-to-analog converter
MUX Multiplexer
NPR Noise power ratio
os Offset voltage (V)
OFDM Orthogonal frequency division multiplexing transmission
PAPR Peak-to-average power ratio
P Power back-off value (dB)
backoff
P Clipping distortion power (W)
c
PCB Printed circuit board
Pdf Probability density function
P ADC full scale signal power measured with a sinusoid (W)
fs
P Noise power (W)
n
P Signal power (W)
s
PSD Power spectral density (W/Hz)
Q(x) Quantization function
QADC Quarter ADC
QAM Quadrature amplitude modulation
R Signal range processed by the ADC
ADC
RMS Root mean square
SAR Successive approximation register
SC Switched capacitor
SCDR Signal to clipping distortion ratio
SymbolsandAbbreviations ix
SelMUX Path selection multiplexer
SFDR Spurious free dynamic range
SHA Sample-and-hold-amplifier
SNCDR Signal to noise and clipping distortion ratio
SNDR Signal to noise and distortion ratio
SNR Signal-to-noise ratio
SoC System on chip
SOI Silicon on insulator
SQNR Signal to quantization noise ratio
STNR Signal to thermal noise ratio
T/H Track and hold
THD Total harmonic distortion
TI-ADC Time interleaving ADC
T Data block duration (sec)
b
T Sampling period (sec)
s
USB Universal serial bus
V Auxiliary path input signal (V)
aux
V Bias voltage (V)
b
V Clock voltage (V)
clk
V Common mode voltage (V)
cm
V Supply voltage (V)
dd
V Input voltage (V)
in
V Main path input signal (V)
main
V RMS noise voltage (V)
n.RMS
V Output voltage (V)
out
V Peak-to-peak differential voltage (V)
ppd
V Reference voltage (V)
r
V Output residue signal voltage (V)
res
V RMS signal voltage (V)
s.RMS
V Threshold voltage (V)
th
VLSI Symposia on VLSI Technology and Circuits
WiMAX Worldwide interoperability for microwave access
WLAN Wireless local area network
WPAN Wireless personal area network
Δt Timing skew (sec)
Δ ADC least significant bit size (V)
LSB
η Voltage efficiency
vol
η Current efficiency
vol
Φ Clock signal