Power Distribution Networks in High Speed Integrated Circuits

286 Pages·2004·9.29 MB·English

by  Andrey V. Mezhiba, Eby G. Friedman (auth.)

Power Distribution Networks
in High Speed Integrated Circuits
POWER DISTRIBUTION NETWORKS
IN HIGH SPEED INTEGRATED CIRCUITS
ANDREY V. MEZHIBA
Department of Electrical and Computer Engineering
University of Rochester
Rochester. New York 14627
USA
EBY G. FRIEDMAN
Department of Electrical and Computer Engineering
University of Rochester
Rochester. New York 14627
USA
.....
"
Springer Science+Business Media, LLC
Library of Congress Cataloging-in-Publication
CIP info ar:
Title: Powcr Distribution Networks in High speed Integrated Circuits
AUlhor (s): Andrey V. Mezhiba and Eby G. Friedman
ISBN 978-1-4613-5057-6 ISBN 978-1-4615-0399-6 (eBook)
DOI 10.1007/978-1-4615-0399-6
e
Copyright 2004 by Springer Science+Business Media New York
Originally publisbed by Kluwer Academic Publisbers in 2004
Softcover reprint ofthe hardcover Ist edition 2004
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Printed on acid-iree paper.
To Elizabeth
To Laurie, Joseph, and Samuel
Contents
List of Figures xiii
List of Tables XIX
Preface XXI
1. INTRODUCTION 1
1.1 Evolution of integrated circuit technology 2
1.2 Evolution of design objectives 5
1.3 The problem of power distribution 8
1.4 Deleterious effects of power distribution noise 13
1.4.1 Signal delay uncertainty 13
1.4.2 On-chip clock jitter 13
1.4.3 Noise margin degradation 15
1.4.4 Degradation of gate oxide reliability 16
1.5 Book outline 16
2. INDUCTIVE PROPERTIES OF ELECTRIC CIRCUITS 21
2.1 Definitions of inductance 22
2.1.1 Field energy definition 22
2.1.2 Magnetic flux definition 24
2.1.3 Partial inductance 29
2.1.4 Net inductance 34
2.2 Variation of inductance with frequency 37
2.2.1 Uniform current density approximation 37
2.2.2 Inductance variation mechanisms 38
2.2.3 Simple circuit model 42
2.3 Inductive behavior of circuits 44
2.4 Inductive properties of on-chip interconnect 47
2.5 Summary 50
Vlll Contents
3. PROPERTIES OF ON-CHIP INDUCTIVE CURRENT
LOOPS 53
3.1 Introduction 53
3.2 Dependence of inductance on line length 54
3.3 Inductive coupling between two parallel loop segments 60
3.4 Application to circuit analysis 62
3.5 Summary 63
4. ELECTRO MIGRATION 65
4.1 Physical mechanism of electromigration 66
4.2 Electromigration-induced mechanical stress 69
4.3 Steady state limit of electromigration damage 69
4.4 Dependence of electromigration lifetime on the line
dimensions 71
4.5 Statistical distribution of electromigration lifetime 74
4.6 Electromigration lifetime under AC current 75
4.7 Electromigration in novel interconnect technologies 76
4.8 Designing for electromigration reliability 78
4.9 Summary 79
5. HIGH PERFORMANCE POWER DISTRIBUTION SYSTEMS 81
5.1 Physical structure of a power distribution system 82
5.2 Circuit model of a power distribution system 83
5.3 Output impedance of a power distribution system 86
5.4 A power distribution system with a decoupling capacitor 89
5.4.1 Impedance characteristics 89
5.4.2 Limitations of a single-tier decoupling scheme 92
5.5 Hierarchical placement of decoupling capacitance 94
5.6 Resonance in power distribution networks 100
5.7 Full impedance compensation 107
5.8 Case study 109
5.9 Design considerations 111
5.9.1 Inductance of the decoupling capacitors 112
5.9.2 Interconnect inductance 113
5.10 Limitations of the one-dimensional circuit model 114
5.11 Summary 116
Contents IX
6. ON-CHIP POWER DISTRIBUTION NETWORKS 119
6.1 Styles of on-chip power distribution networks 120
6.1.1 Basic structure of on-chip power distribution
networks 120
6.1.2 Improving the impedance characteristics of
on-chip power distribution networks 125
6.1.3 Evolution of power distribution networks
in Alpha microprocessors 126
6.2 Allocation of on-chip decoupling capacitance 128
6.2.1 Types of on-chip decoupling capacitance 128
6.2.2 Allocation strategies 132
6.2.3 On-chip switching voltage regulator 136
6.3 Die-package interface 138
6.4 Other considerations 143
6.5 Summary 144
7. COMPUTER-AIDED DESIGN AND ANALYSIS 147
7.1 Design flow for on-chip power distribution networks 148
7.2 Linear analysis of power distribution networks 153
7.3 Modeling power distribution networks 154
7.4 Characterizing the power current requirements
of on-chip circuits 160
7.5 Numerical methods for analyzing power distribution
networks 163
7.6 Summary 169
8. INDUCTIVE PROPERTIES OF ON-CHIP POWER
DISTRIBUTION GRIDS 171
8.1 Power transmission circuit 171
8.2 Simulation setup 174
8.3 Grid types 174
8.4 Inductance versus line width 176
8.5 Dependence of inductance on grid type 180
8.5.1 Non-interdigitated versus interdigitated grids 180
8.5.2 Paired versus interdigitated grids 181
8.6 Dependence of Inductance on grid dimensions 181
8.6.1 Dependence of inductance on grid width 182
8.6.2 Dependence of inductance on grid length 183
8.6.3 Sheet inductance of power grids 184
x Contents
8.6.4 Efficient computation of grid inductance 184
8.7 Summary 186
9. VARIATION OF GRID INDUCTANCE WITH FREQUENCY 187
9.1 Analysis approach 187
9.2 Discussion of inductance variation 189
9.2.1 Circuit models 189
9.2.2 Analysis of inductance variation 192
9.3 Summary 194
10. INDUCTANCE/AREA/RESISTANCE TRADEOFFS 197
10.1 Inductance vs. resistance tradeoff under a constant
grid area constraint 197
10.2 Inductance vs. area tradeoff under a constant grid
resistance constraint 201
10.3 Summary 204
11. SCALING TRENDS OF ON-CHIP POWER DISTRIBUTION
NOISE 205
11.1 Prior work 206
11. 2 Interconnect characteristics 209
11.2.1 Global interconnect characteristics 209
11.2.2 Scaling of the grid inductance 210
11.2.3 Flip-chip packaging characteristics 211
11.2.4 Impact of on-chip capacitance 212
11.3 Model of power supply noise 214
11.4 Power supply noise scaling 215
11.4.1 Analysis of constant metal thickness scenario 215
11.4.2 Analysis of the scaled metal thickness scenario 217
11.4.3 ITRS scaling of power noise 218
11.5 Implications of noise scaling 222
11.6 Summary 223
12. IMPEDANCE CHARACTERISTICS OF MULTI-LAYER
GRIDS 225
12.1 Electrical properties of multi-layer grids 227
12.1.1 Impedance characteristics of individual grid layers 227
12.1.2 Impedance characteristics of multi-layer grids 229
12.2 Case study of a two layer grid 232
12.2.1 Simulation setup 232
Contents Xl
12.2.2 Inductive coupling between grid layers 233
12.2.3 Inductive characteristics of a two layer grid 236
12.2.4 Resistive characteristics of a two layer grid 237
12.2.5 Variation of impedance with frequency
in a two layer grid 239
12.3 Design implications 240
12.4 Summary 241
13. INDUCTIVE EFFECTS IN ON-CHIP POWER
DISTRIBUTION NETWORKS 243
13.1 Scaling effects in chip-package resonance 244
13.2 Propagation of power distribution noise 246
13.3 Local inductive behavior 248
13.4 Summary 252
14. CONCLUSIONS 255
References 259
Index 275
About the Authors 279
List of Figures
1.1 Evolution of transistor count of microprocessors
and memory ICs. 3
1.2 Evolution of microprocessor clock frequency. 4
1.3 Evolution of design criteria in CMOS integrated
circuits. 6
1.4 Evolution of microprocessor power consumption. 7
1.5 Basic power delivery system. 8
1.6 Evolution of the average current in high perfor-
mance microprocessors. 9
1.7 Increase in power current of microprocessors with
technology scaling. 10
1.8 Scaling of the CMOS noise margins. 11
1.9 A grid structured power distribution network. 12
1.10 Cycle-to-cycle jitter of a clock signal. 14
1.11 Peak-to-peak jitter of a clock signal. 15
2.1 Two complete current loops. 25
2.2 A circuit with branch points. 28
2.3 Two segmented current loops. 30
2.4 A straight round wire. 31
2.5 Self and mutual partial inductance of a straight
segment of wire. 33
2.6 Loop magnetic flux in terms of partial fluxes. 35
2.7 The signal and return current paths. 36
2.8 Internal magnetic flux of a round conductor. 39
2.9 Proximity effect in two closely spaced lines. 39