Pipelined ADC Design and Enhancement Techniques

225 Pages·2010·2.9 MB·English

by  Imran Ahmed (auth.)

Analog Circuits and Signal Processing
Forfurthervolumes:
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PipelinedADC Designand Enhancement Techniques
Consulting Editor:MohammedIsmail. OhioState University
Imran Ahmed
Pipelined ADC Design and
Enhancement Techniques
Dr.ImranAhmed
KapikIntegration
192SpadinaAve.
TorontoM5T2C2
Suite218
Canada
[email protected]
ISBN978-90-481-8651-8 e-ISBN978-90-481-8652-5
DOI10.1007/978-90-481-8652-5
SpringerHeidelbergDordrechtLondonNewYork
LibraryofCongressControlNumber:2010920320
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Preface
PipelinedADCshaveseenatremendousgrowthininnovationandscopeoverthe
pastfewyears.Assuchunderstandingboththebasicconceptsandtheleadingedge
techniques required to realize pipelined ADCs which meet the challenging speci-
ficationsoftoday’smarketandapplicationsisrequired.WhilepipelinedADCsare
popular circuit blocks, beyond publications in periodicals there are only a few
condensedresourceswhicharededicatedtoeducationinthearea.Thisbookaimsto
helpbridgethegapwithathoroughdiscussionofpipelinedADCs.
This book is targeted to both the beginner and expert looking to acquire
knowledgeinpipelinedADCs.Inthefirstsectionofthisbook,atutorialdiscussion
ofseveralkeydesigntradeoffsinvolvedindesigningapipelinedADCisgiven.The
discussion is presented with sufficient detail so as to allow those with only intro-
ductory knowledge of pipelined ADCs to quickly understand the limiting factors
whichmotivateresearchintomethodswhichenhancetheperformanceofpipelined
ADCs. In the second half of this book a detailed overview and discussion of four
state-of-the-artpipelinedADCswithsiliconimplementationsandmeasuredresults
is given. The innovations include: a technique to rapidly digitally correct gain +
DAC errors in a pipelined ADC, an architecture to enable a single ADC to be
designed to achieve low power for a very wide range of sampling rates, a circuit
techniquetoeliminatefront-endsample-and-holdsinpipelinedADCs,andfinallya
verylowpowerpipelinedADCarchitecturebasedoncapacitivechargepumps.
The innovations presented in this book provides several tools which can be of
great use to help a pipelined ADC designer deliver a design with good linearity,
broadapplication,andverylowpower.
v
Acknowledgements
Research is a unique proposition. One is forced to look into the depths of the
unknownandfindananswertoaquestionthatdoesnotnecessarilyhaveananswer.
In some cases your answer fits the question – in some cases your answer fits the
questionlikeasquarepeginaroundhole.Regardlessofthemadness,thejourney
of developing abstract ideas into ultimately something which works is truly a
unique and completely enriching experience – an experience that I for one am
tremendouslythankfulforandveryfortunatetohaveundergoneindevelopingthe
material for this book. Acknowledging specific people in the development of an
abstractpieceofartissomewhatpartial,asundoubtedlyeverypersononeinteracts
withduringthecourseofawritingabookinsomeshapeorformimpactsthework.
Thereareafewkeypeoplehoweverwhohavehelpedthisworktakeform.Firstly
I must thank Professor DavidJohns at the University of Toronto. His guidance in
developing many of the ideas discussed in this book were invaluable. I am also
thankful to Professor Ken Martin, also of the University of Toronto, whose rigor
andboldnesssignificantlyhelpedthisworktakeshape.Ialsothankthesupportof
the team of excellent designers at Broadcom Netherlands, especially Jan Mulder
andKlaasBult,whoinadditiontoprovidingawealthofknowledge,haveinspired
me to be excited about the future in mixed signal circuit design. Of course one
cannotaccomplishanythinginlifewithouttheunquestionedpillarofsupportone’s
familyoffers.Thisbookisdedicatedtomyfamily.
vii
Contents
1 Introduction ............................................................... 1
1.1 Overview ............................................................... 1
1.2 ChapterOutline ........................................................ 3
1.2.1 SectionI:PipelinedADCDesign .............................. 3
1.2.2 SectionII:PipelinedADCEnhancementTechniques ......... 4
PartI PipelinedADCDesign
2 ADCArchitectures ....................................................... 7
2.1 Overview ............................................................... 7
2.2 FactorsWhichDetermineADCResolutionandLinearity ............ 7
2.3 ADCArchitectures ................................................... 11
2.4 ADCFigure-of-Merit ................................................. 12
2.5 FlashADC ............................................................ 12
2.6 SARADC ............................................................. 14
2.7 Sub-sampling ......................................................... 16
2.8 Summary .............................................................. 17
3 PipelinedADCArchitectureOverview ................................ 19
3.1 Overview .............................................................. 19
3.2 PipelinedADCIntroduction .......................................... 19
3.3 MultiplyingDigitaltoAnalogConverter(MDAC) .................. 21
3.4 OpampDCGainRequirements ...................................... 23
3.5 OpampBandwidthRequirements .................................... 26
3.6 ThermalNoiseRequirements ......................................... 28
3.7 MDACDesign:CapacitorMatching/Linearity ...................... 29
3.8 ErrorCorrectioninPipelinedADCs:RelaxedSub-ADC
Requirements ......................................................... 31
3.9 Sub-ADCDesign:Comparator ....................................... 35
3.10 Front-EndSample-and-Hold ........................................ 36
3.11 Summary ............................................................. 38
ix
x Contents
4 ScalingPowerwithSamplingRateinanADC ........................ 39
4.1 Overview .............................................................. 39
4.2 ADCPowerasaFunctionofSamplingRate ........................ 39
4.3 DigitalVersusAnalogPower ......................................... 40
4.4 WeakInversionModel:EKV ........................................ 42
4.5 WeakInversionIssues:Mismatch .................................... 43
4.6 CurrentScaling:MultipleDesignCorners ........................... 45
4.7 CurrentScaling:BiasPointSensitivity .............................. 45
4.8 CurrentScaling:IRDrops ............................................ 46
4.9 Summary .............................................................. 48
5 StateoftheArtPipelinedADCDesign ................................ 49
5.1 Overview .............................................................. 49
5.2 CalibrationinPipelinedADCs ....................................... 49
5.2.1 ReviewofErrorSources ....................................... 50
5.2.2 GainErrorCorrection ......................................... 50
5.2.3 DACErrorCorrection ......................................... 52
5.2.4 ForegroundCalibration ........................................ 52
5.2.5 BackgroundCalibration ....................................... 53
5.2.6 RapidCalibrationofADCErrors ............................. 54
5.3 PowerScalabilitywithRespecttoSamplingRate ................... 56
5.4 PowerReductionTechniquesinPipelinedADCs .................... 56
5.4.1 Front-EndS/HRemoval ....................................... 56
5.4.2 Open-LoopAmplifierApproach ............................... 58
5.4.3 ComparatorBasedSwitchedCapacitorCircuits .............. 60
5.5 Summary .............................................................. 61
PartII PipelinedADCEnhancementTechniques
6 RapidCalibrationofDACandGainErrorsinaMulti-bit
PipelineStage ............................................................ 65
6.1 Overview .............................................................. 65
6.2 Motivation ............................................................ 65
6.2.1 WhyAreDACErrorsImportanttoCorrect? ................. 66
6.3 RapidDAC+GainCalibrationArchitecture ........................ 66
6.3.1 MeasurementofMissingCodesDuetoDAC
andGainErrors ................................................ 67
6.3.2 CorrectionofMissingCodes .................................. 68
6.3.3 MismatchBetweenADCs ..................................... 69
6.3.4 SimulationResults ............................................. 70
6.4 CircuitImplementation ............................................... 73
6.4.1 Front-EndSample-and-Hold ................................... 74
6.4.2 5-BitFlashADC ............................................... 75
Contents xi
6.4.3 4-BitMDAC ................................................... 75
6.4.4 BackendPipelinedADC ....................................... 77
6.4.5 DigitalCalibration ............................................. 78
6.5 Testing ................................................................ 78
6.5.1 PCB ............................................................ 79
6.5.2 TestSetup ...................................................... 79
6.6 MeasuredResults ..................................................... 81
6.6.1 INL/DNLPlots ................................................ 81
6.6.2 SNDR/SFDRPlots ............................................. 81
6.6.3 CalibrationTime ............................................... 82
6.7 Summary .............................................................. 84
7 APowerScalableandLowPowerPipelinedADC .................... 85
7.1 Overview .............................................................. 85
7.2 PowerScalableArchitecture ......................................... 85
7.3 CurrentModulatedPowerScaling(CMPS) .......................... 88
7.4 CurrentSwitchingIssues ............................................. 91
7.5 HybridPowerScaling ................................................ 92
7.6 DetailedTriggerAnalysis ............................................ 93
7.7 DesignoftheDigitalStateMachine ................................. 97
7.8 RapidPower-OnOpamps ........................................... 100
7.8.1 ConventionalApproach:SwitchedBiasOpamp ............. 100
7.8.2 RapidPower-OnOpampsUsedinThisWork ............... 101
7.8.3 BenefitsofFeedbackBasedBiasing:IncreasedOutput
Resistance ..................................................... 104
7.8.4 OpampSpecification/Characterization ....................... 105
7.9 CommonModeFeedBack(CMFB)forRapid
Power-OnOpamp ................................................... 109
7.10 PowerReductionThroughCurrentModulation .................. 111
7.10.1 CommonModeFeedBack(CMFB)for
DifferentOpampModes .................................. 112
7.11 Sample-and-Hold(S/H) ........................................... 113
7.12 1.5-bitMDAC ..................................................... 114
7.13 Sub-ADCComparators ............................................ 114
7.14 BiasCircuits ....................................................... 115
7.15 Non-overlappingClockGenerator ................................ 116
7.16 Referencevoltages ................................................ 117
7.17 DigitalErrorCorrection ........................................... 118
7.18 ExperimentalImplementation:PCB .............................. 118
7.19 ExperimentalImplementation:TestSetup ........................ 118
7.20 MeasuredResults .................................................. 120
7.21 CurrentScaledPower ............................................. 121
7.21.1 PowerReductionMode:StaticAccuracy ................. 127
7.21.2 PowerScalableADC:CurrentScaling ................... 131