Table Of Content

4 3 2 1 D D PAGE 1: TABLE OF CONTENTS PAGE 2: <<BLANK>> PAGE 3: <<BLANK>> PAGE 4: <<BLANK>> PAGE 5: BANK0: SYSACE, LCD, SPI PAGE 6: BANK1: PM I/O, UART, DEBUG LED, I2C PAGE 7: BANK2: PCI BUS, RESET, INTR PAGE 8: BANK3: PM LVDS IO PAGE 9: BANK4: TRACE, CPU DEBUG, PM I/O NOTE: PLEASE REVIEW THE ML310 BOM FOR ITEMS DESIGNATED AS "NOSTUFF". PAGE 10: BANK5: DDR PAGE 11: BANK6: DDR NOSTUFF ITEMS ARE NOT POPULATED ON THE PCB. C PAGE 12: BANK7: DDR C PAGE 13: FPGA CONFIG AND MISC I/O THE ML310 BOM CONTAINS THE MOST ACCURATE INFORMATION ABOUT PAGE 14: FPGA DECOUPLING PAGE 15: MGT POWER SUPPLIES NOSTUFF DISCRETES AND COMPONENTS. PAGE 16: TOP MGT TRANSCEIVERS PAGE 17: BOT MGT TRANSCEIVERS PAGE 18: PERSONALITY MODULE CONNECTORS PAGE 19: JTAG, DEBUG, TRACE CONNECTORS PAGE 20: SYSTEM ACE AND COMPACT FLASH PAGE 21: DDR DIMM CONNECTOR PAGE 22: DDR SSTL-2 TERMINATION PAGE 23: DDR TERMINATION SUPPLY XILINX PART NUMBERS PAGE 24: PCI BUS PULLUPS PAGE 25: PCI-PCI BRIDGE PAGE 26: PCI SLOT 6, 5.0V, SECONDARY BUS PAGE 27: PCI SLOT 5, 3.3V, PRIMARY BUS PAGE 28: PCI SLOT 4, 5.0V, SECONDARY BUS SCHEMATICS 0381171-02 PAGE 29: PCI SLOT 3, 3.3V, PRIMARY BUS PAGE 30: << BLANK >> B B PCB ARTWORK 0531311-02 PAGE 31: PCI ETHERNET MAC/PHY PAGE 32: PCI ETHERNET INTERFACE, PROM PAGE 33: PCI SOUTH BRIDGE, PART 1 PCB FABRICATION 1280333-02 PAGE 34: PCI SOUTH BRIDGE, PART 2-3 PAGE 35: PCI SOUTH BRIDGE, PART 4-5 PAGE 36: PCI SOUTH BRIDGE, CONFIG RESISTORS PAGE 37: PCI SOUTH BRIDGE, UNUSED PIN RESISTORS PAGE 38: PARALLEL PORT INTERFACE PAGE 39: RS232 SERIAL PORT INTERFACE PAGE 40: KBD/MOUSE AND USB INTERFACES PAGE 41: IDE INTERFACES PAGE 42: SOUTH BRIDGE ROM AND GPIO PAGE 43: AC97 CODEC PAGE 44: AC97 CONNECTORS SCH P/N 0381171-02 PAGE 45: I2C AND SPI DEVICES ART P/N 0531311-02 PAGE 46: DEBUG AND STATUS LEDS FAB P/N 1280333-02 PAGE 47: ATX AND FRONT PANEL CONNECTORS PAGE 48: RESET SWITCHES AND FPGA SERIAL PORT Title: ML310 VIRTEX-II PRO PLAFTORM A PAGE 49: ATX CONNECTOR AND DC-DC CONVERTORS TABLE OF CONTENTS PAGE 50: POWER SUPPLY MONITORS AND LEDS A PAGE 51: ATX MOUNTING HOLES AND TEST POINTS Date: 6-4-2004_12:54 Ver: X.X PAGE 52: FPGA FAN SWITCH AND TACH Sheet Size: B Rev: X Sheet 1 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 2 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 3 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 4 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK0 VCC2V5 FF896 R374 (DIE DOWN) VRN_BANK0 U37 5 49.9 5 VRN_BANK0 E24 IO_L01P_0/VRN_0_E24 5 VRP_BANK0 E25 IO_L01N_0/VRP_0_E25 VCC2V5 D D R385 VRP_BANK0 SYSACE_MPIRQ F23 J18 5 20 IO_L02P_0_F23 VCCO_0_J18 SYSACE_MPBRDY F24 J19 20 IO_L02N_0_F24 VCCO_0_J19 49.9 20 SYSACE_MPCE E22 IO_L03P_0/VREF_0_E22 VCCO_0_J20 J20 SYSACE_MPOE E23 J21 20 IO_L03N_0_E23 VCCO_0_J21 SYSACE_MPWE G23 K16 20 IO_L05_0/No_Pair_G23 VCCO_0_K16 SYSACE_MPD15 G22 K17 20 IO_L06P_0_G22 VCCO_0_K17 SYSACE_MPD14 H22 K18 20 IO_L06N_0_H22 VCCO_0_K18 SYSACE_MPD13 F21 K19 20 IO_L07P_0_F21 VCCO_0_K19 VCC2V5 20 SYSACE_MPD12 F22 IO_L07N_0_F22 VCCO_0_K20 K20 SYSACE_MPD11 C24 K21 20 IO_L08P_0_C24 VCCO_0_K21 SYSACE_MPD10 D24 20 IO_L08N_0_D24 SYSACE_MPD09 G21 20 IO_L09P_0/VREF_0_G21 SYSACE_MPD08 H21 2 J17 R28 80.6 222000 SSYYSSAACCEE__MMPPDD0067 ED2211 IIIOOO___LLL033977NNP___000___HED222111 SYSACE_MPD05 C23 20 IO_L38P_0_C23 3 SYSACE_MPD04 D23 20 IO_L38N_0_D23 1 USER_SMA_CLK SYSACE_MPD03 G20 5 20 IO_L39P_0_G20 4 SYSACE_MPD02 H20 20 IO_L39N_0_H20 SYSACE_MPD01 D20 CO5N_SMA_ST R407 130 222000 SSYYSSAACCEE__MMPPAD0060 EA2203 IIIOOO___LLL444334NPP___000___EDA222003 SYSACE_MPA05 B23 20 IO_L44N_0_B23 SYSACE_MPA04 G19 20 IO_L45P_0/VREF_0_G19 SYSACE_MPA03 H19 20 IO_L45N_0_H19 SYSACE_MPA02 E18 20 IO_L46P_0_E18 C SYSACE_MPA01 E19 C 20 IO_L46N_0_E19 SYSACE_MPA00 B22 20 IO_L47P_0_B22 SYSACE_CLK_OE C22 9 IO_L47N_0_C22 FPGA_LCD_DB0 F19 47 IO_L48P_0_F19 FPGA_LCD_DB1 F20 47 IO_L48N_0_F20 FPGA_LCD_DB2 F17 47 IO_L49P_0_F17 FPGA_LCD_DB3 G17 47 IO_L49N_0_G17 FPGA_LCD_DB4 B21 47 IO_L50_0/No_Pair_B21 FPGA_LCD_DB5 A21 47 IO_L53_0/No_Pair_A21 FPGA_LCD_DB6 G18 47 IO_L54P_0_G18 FPGA_LCD_DB7 H18 47 IO_L54N_0_H18 FPGA_LCD_DIR C20 47 IO_L56P_0_C20 FPGA_LCD_E C21 46 IO_L56N_0_C21 FPGA_LCD_RW H17 46 IO_L57P_0/VREF_0_H17 NOTE: 130 OHM RESISTORS ON EG-2121 OUTPUTS ARE FPGA_LCD_RS J17 46 IO_L57N_0_J17 PM_IO_78 D17 18 IO_L67P_0_D17 INTENDED TO PROVIDE A LOAD FOR THE PECL PM_IO_79 E17 18 IO_L67N_0_E17 PM_IO_80 C18 18 IO_L68P_0_C18 DRIVERS AND SHOULD BE PLACED NEAR THE OSC. PM_IO_81 D18 18 IO_L68N_0_D18 PM_IO_82 H16 18 IO_L69P_0/VREF_0_H16 PM_IO_83 J16 18 IO_L69N_0_J16 VCC2V5 NC D16 IO_L73P_0_D16 FPGA_CPU_RESET_N E16 48 IO_L73N_0_E16 FB5 R400 X7 1 6 LVDS_CLKLOC_P F16 OE VCC 5,10 IO_L75P_0/GCLK4S_F16 BLM18AG LVDS_CLKLOC_N G16 4.75K 5,10 IO_L75N_0/GCLK5P_G16 PM_CLK_TOP B16 B 18 IO_L74P_0/GCLK6S_B16 B C193 C194 C184 2 5 LVDS_CLKLOC1_N USER_SMA_CLK C16 NC OSC N 5 IO_L74N_0/GCLK7P_C16 0.1UF 0.1UF 10UF 6.3V 3 4 LVDS_CLKLOC1_P GND P EG-2121CA NOTE: IN ORDER TO FACILITATE TEST POINT INSERTION FOR 156.2500MHZ R402 130 R401 130 1 BGA PACKAGE DEVICES, THE UNUSED PINS ON THE BGAS 2 LVDS_CLKLOC_P 5,10 ARE TIED TO AN "UNUSED PIN" NET EVEN THOUGH THEY 3 APPEAR TO BE NO-CONNECTS IN THE SCHEMATIC. PLEASE J20 CHECK THE NETLISTS BEFORE MODIFYING ANY NC PINS ON 1 A BGA PACKAGE TO ENSURE THE LAYOUT AND SCHEMATIC VCC2V5 2 LVDS_CLKLOC_N REMAIN CONSISTENT. 5,10 FB16 R417 X9 3 1 6 OE VCC BLM18AG 4.75K J21 SCH P/N 0381171-02 ART P/N 0531311-02 C212 C213 C207 2 5 LVDS_CLKLOC2_N FAB P/N 1280333-02 NC OSC N 0.1UF 0.1UF 10UF 6.3V 3 4 LVDS_CLKLOC2_P Title: ML310 VIRTEX-II PRO PLAFTORM GND P A EG-2121CA BANK0: SYSACE, LCD, SPI 125.0000MHZ R419 130 R418 130 A Date: 6-4-2004_12:58 Ver: X.X Sheet Size: B Rev: X Sheet 5 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK1 FF896 (DIE DOWN) VCC3_PCI U37 VRN_BANK1 E6 6 IO_L01P_1/VRN_1_E6 R431 6 VRP_BANK1 E7 IO_L01N_1/VRP_1_E7 VCC3_PCI VRN_BANK1 D 6 D 49.9 18 PM_IO_3V_0 F7 IO_L02P_1_F7 VCCO_1_J10 J10 PM_IO_3V_1 F8 J11 18 IO_L02N_1_F8 VCCO_1_J11 PM_IO_3V_2 E8 J12 18 IO_L03P_1_E8 VCCO_1_J12 R428 18 PM_IO_3V_3 E9 IO_L03N_1/VREF_1_E9 VCCO_1_J13 J13 VRP_BANK1 G8 K10 6 NC IO_L05_1/No_Pair_G8 VCCO_1_K10 PM_IO_3V_4 H9 K11 18 IO_L06P_1_H9 VCCO_1_K11 49.9 18 PM_IO_3V_5 G9 IO_L06N_1_G9 VCCO_1_K12 K12 PM_IO_3V_6 F9 K13 18 IO_L07P_1_F9 VCCO_1_K13 PM_IO_3V_7 F10 K14 18 IO_L07N_1_F10 VCCO_1_K14 PM_IO_3V_8 D7 K15 18 IO_L08P_1_D7 VCCO_1_K15 PM_IO_3V_9 C7 18 IO_L08N_1_C7 PM_IO_3V_10 H10 18 IO_L09P_1_H10 PM_IO_3V_11 G10 18 IO_L09N_1/VREF_1_G10 PM_IO_3V_12 E10 18 IO_L37P_1_E10 PM_IO_3V_13 D10 18 IO_L37N_1_D10 VCC5V 18 PM_IO_3V_14 D8 IO_L38P_1_D8 VCC3_PCI 18 PM_IO_3V_15 C8 IO_L38N_1_C8 PM_IO_3V_16 H11 18 IO_L39P_1_H11 U41 PM_IO_3V_17 G11 18 IO_L39N_1_G11 8 1 PM_IO_3V_18 E11 IN OUT 18 IO_L43P_1_E11 PM_IO_3V_19 D11 18 IO_L43N_1_D11 5 SHDN GND33 18 PM_IO_3V_20 B8 IO_L44P_1_B8 C236 PM_IO_3V_21 A8 1 18 IO_L44N_1_A8 C 2120UVF NC 42 BYPADJ GGNNDD6776 R455 38.3 1206 2 C362..3337UVF 11118888 PPPPMMMM____IIIIOOOO____3333VVVV____22222345 EEGH11113222 IIIIOOOO____LLLL44446655NPNP____1111__/_EEVH11R132E2F_1_G12 C LT1763CS8 C9 NC IO_L47P_1_C9 JTAG_SRC_SEL B9 19 IO_L47N_1_B9 F11 NC IO_L48P_1_F11 UART0_TXD F12 48 IO_L48N_1_F12 UART0_RTS_N G14 R454 26.1 1206 444888 UUAARRTT00__CRTXSD_N NC ABF111004 IIIIOOOO____LLLL55443099__NP11__//11NN__ooFG__11PP44aaiirr__AB1100 DBG_LED_0 H13 46 IO_L54P_1_H13 DBG_LED_1 G13 46 IO_L54N_1_G13 DBG_LED_2 C10 46 IO_L56P_1_C10 DBG_LED_3 C11 46 IO_L56N_1_C11 DBG_LED_4 J14 46 IO_L57P_1_J14 NOTE: THE COMPONENT VALUES FOR THIS REGULATOR ARE TAKEN DBG_LED_5 H14 46 IO_L57N_1/VREF_1_H14 DBG_LED_6 E14 46 IO_L67P_1_E14 FROM XAPP653. THIS DESIGN IS INTENDED TO SINK CURRENT DBG_LED_7 D14 46 IO_L67N_1_D14 D13 NC IO_L68P_1_D13 THROUGH THE 1206 RESISTORS WHEN THE CLAMP DIODES ON FPGA_SCL C13 6 IO_L68N_1_C13 FPGA_SDA J15 6 IO_L69P_1_J15 THE FPGA ARE CONDUCTING DURING OVERSHOOT. THIS IS WHY IIC_ALERT_N H15 35,45 IO_L69N_1/VREF_1_H15 IIC_IRQ_N E15 THE VALUES ARE UNUSUAL RELATIVE TO THE LT1763 DATASHEET. 45 IIC_THERM_N D15 IO_L73P_1_E15 35,45 IO_L73N_1_D15 PCI_P_CLK5 C15 7 IO_L74P_1/GCLK0S_C15 USER_CLKPCI B15 6 IO_L74N_1/GCLK1P_B15 LVDS_CLKEXT_P G15 B 9,18 IO_L75P_1/GCLK2S_G15 B LVDS_CLKEXT_N F15 R426 9,18 IO_L75N_1/GCLK3P_F15 IIC_SCL FPGA_SCL 21,35,45 6 0 R427 IIC_SDA FPGA_SDA 21,35,45 6 0 VCC3V3 R448 X10 1 14 OE1 VCC1 4.75K OSC C581 0.1UF 4 11 OE2 VCC2 SCH P/N 0381171-02 ART P/N 0531311-02 R447 7 8 USER_CLKPCI_R USER_CLKPCI FAB P/N 1280333-02 GND OUT 6 24.9 SG-531PCW 33.0000MHZ Title: ML310 VIRTEX-II PRO PLAFTORM A NOSTUFF NOTE: X10 IS REPLACED WITH A 100MHZ 3.3V OSCILLATOR BANK1: PM I/O, UART, DEBUG LED, I2C XS10 AND IS USED AS THE PRIMARY FPGA REFCLK INPUT ON A SOCKETED Date: 1-5-2004_13:05 Ver: X.X 14-PIN DIP PRODUCTION BOARDS AS A LOWER COST ALTERNATIVE TO Sheet Size: B Rev: X USING A 100MHZ 2.5V OSCILLATOR IN LOCATION X6. Sheet 6 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK2 FF896 (DIE DOWN) VCC3_PCI U37 VRN_BANK2 B3 7 IO_L01P_2/VRN_2_B3 R38 7 VRP_BANK2 A3 IO_L01N_2/VRP_2_A3 VCC3_PCI VRN_BANK2 D 7 R2 D PCI_P_CLK0 7,27 49.9 25,27,29,31,33 PCI_P_AD00 G5 IO_L02P_2_G5 VCCO_2_J9 J9 4.75K PCI_P_AD01 G6 K9 25,27,29,31,33 IO_L02N_2_G6 VCCO_2_K9 PCI_P_AD02 D5 L9 25,27,29,31,33 IO_L03P_2_D5 VCCO_2_L9 R1 R35 25,27,29,31,33 PCI_P_AD03 C5 IO_L03N_2_C5 VCCO_2_L10 L10 7,29 PCI_P_CLK1 VRP_BANK2 PCI_P_AD04 C1 M9 7 25,27,29,31,33 IO_L04P_2_C1 VCCO_2_M9 4.75K PCI_P_AD05 C2 M10 25,27,29,31,33 IO_L04N_2/VREF_2_C2 VCCO_2_M10 49.9 25,27,29,31,33 PCI_P_AD06 J7 IO_L05P_2_J7 VCCO_2_N9 N9 R200 PCI_P_AD07 J8 N10 PCI_P_CLK2 25,27,29,31,33 IO_L05N_2_J8 VCCO_2_N10 7,31 PCI_P_AD08 D3 P10 25,27,29,31,33 IO_L06P_2_D3 VCCO_2_P10 4.75K PCI_P_AD09 C4 R10 25,27,29,31,33 IO_L06N_2_C4 VCCO_2_R10 PCI_P_AD10 D1 25,27,29,31,33 IO_L31P_2_D1 R164 PCI_P_AD11 D2 PCI_P_CLK3 25,27,29,31,33 IO_L31N_2_D2 7,33 PCI_P_AD12 H5 25,27,29,31,33 IO_L32P_2_H5 4.75K PCI_P_AD13 H6 25,27,29,31,33 IO_L32N_2_H6 PCI_P_AD14 E3 25,27,29,31,33 IO_L33P_2_E3 R382 PCI_P_AD15 E4 PCI_P_CLK4 25,27,29,31,33 IO_L33N_2_E4 7,25 PCI_P_AD16 E1 25,27,29,31,33 IO_L34P_2_E1 4.75K PCI_P_AD17 E2 25,27,29,31,33 IO_L34N_2/VREF_2_E2 PCI_P_AD18 K7 25,27,29,31,33 IO_L35P_2_K7 R439 PCI_P_AD19 K8 PCI_P_CLK5 25,27,29,31,33 IO_L35N_2_K8 6,7 PCI_P_AD20 F3 25,27,29,31,33 IO_L36P_2_F3 4.75K PCI_P_AD21 F4 25,27,29,31,33 IO_L36N_2_F4 PCI_P_AD22 F1 25,27,29,31,33 IO_L37P_2_F1 PCI_P_AD23 F2 25,27,29,31,33 IO_L37N_2_F2 PCI_P_AD24 J5 7,25,27,29,31,33 IO_L38P_2_J5 PCI_P_AD25 J6 25,27,29,31,33 IO_L38N_2_J6 C PCI_P_AD26 G3 C 25,27,29,31,33 IO_L39P_2_G3 PCI_P_AD27 G4 NOTE: THE PCI SPEC RECOMMENDS THAT 25,27,29,31,33 IO_L39N_2_G4 PCI_P_AD28 G1 25,27,29,31,33 IO_L40P_2_G1 PCI_P_AD29 G2 CLOCKS BE PULLED LOW WHEN THE 25,27,29,31,33 IO_L40N_2/VREF_2_G2 PCI_P_AD30 L7 25,27,29,31,33 IO_L41P_2_L7 PCI_P_AD31 L8 BUS IS NOT ACTIVELY CLOCKED. 25,27,29,31,33 IO_L41N_2_L8 PCI_P_PAR H3 25,27,29,31,33 IO_L42P_2_H3 H4 NC IO_L42N_2_H4 PCI_P_CBE0_N J2 25,27,29,31,33 IO_L43P_2_J2 PCI_P_CBE1_N H2 25,27,29,31,33 IO_L43N_2_H2 PCI_P_CBE2_N M7 25,27,29,31,33 IO_L44P_2_M7 PCI_P_CBE3_N M8 NOTE: PCI_CLK RESISTORS ALLOW CLOCK TERMINATION 25,27,29,31,33 IO_L44N_2_M8 K5 NC IO_L45P_2_K5 PCI_P_FRAME_N K6 TO BE ADJUSTED INDEPENDENTLY OF OTHER I/O. 24,25,27,29,31,33 IO_L45N_2_K6 PCI_P_IRDY_N K1 24,25,27,29,31,33 IO_L46P_2_K1 PCI_P_TRDY_N J1 24,25,27,29,31,33 IO_L46N_2/VREF_2_J1 PCI_P_STOP_N M5 24,25,27,29,31,33 IO_L47P_2_M5 PCI_P_DEVSEL_N M6 24,25,27,29,31,33 IO_L47N_2_M6 R50 PCI_P_PERR_N J3 PCI_P_CLK0_R PCI_P_CLK0 24,25,27,29,31 IO_L48P_2_J3 7 7,27 PCI_P_SERR_N J4 24,25,27,29,31,33 IO_L48N_2_J4 24.9 PCI_P_LOCK_N L2 24,25,27,29 IO_L49P_2_L2 PCI_FPGA_IDSEL K2 7 IO_L49N_2_K2 R49 N7 PCI_P_CLK1_R PCI_P_CLK1 NC IO_L50P_2_N7 7 7,29 PCI_P_RST_N N8 24,25,27,29,31 IO_L50N_2_N8 24.9 IIC_RESET_N K3 45 IO_L51P_2_K3 SBR_PWG K4 33 IO_L51N_2_K4 R436 SBR_RSM_RSTJ M1 PCI_P_CLK2_R PCI_P_CLK2 35 IO_L52P_2_M1 7 7,31 SBR_IDE_RST_N L1 B 41 IO_L52N_2/VREF_2_L1 24.9 B N5 NC IO_L53P_2_N5 SBR_INTR N6 33 IO_L53N_2_N6 R434 SBR_NMI L4 PCI_P_CLK3_R PCI_P_CLK3 33 IO_L54P_2_L4 7 7,33 PCI_P_INTA_N L5 24,27,29,33 IO_L54N_2_L5 24.9 PCI_P_INTB_N N2 24,27,29,33 IO_L55P_2_N2 PCI_P_INTC_N M2 24,27,29,31,33 IO_L55N_2_M2 R438 PCI_P_INTD_N R9 PCI_P_CLK4_R PCI_P_CLK4 24,27,29,33 IO_L56P_2_R9 7 7,25 PCI_S_INTA_N P9 24,26,28,33 IO_L56N_2_P9 24.9 PCI_S_INTB_N M3 24,26,28,33 IO_L57P_2_M3 M4 NC IO_L57N_2_M4 R437 PCI_P_REQ0_N P1 PCI_P_CLK5_R PCI_P_CLK5 24,27 IO_L58P_2_P1 7 6,7 PCI_P_REQ1_N N1 24,29 IO_L58N_2/VREF_2_N1 24.9 PCI_P_REQ2_N P7 24,31 IO_L59P_2_P7 PCI_P_REQ3_N P8 24,33,36 IO_L59N_2_P8 PCI_P_REQ4_N N3 24,25 IO_L60P_2_N3 N4 NC IO_L60N_2_N4 PCI_P_GNT0_N P2 24,27 IO_L85P_2_P2 PCI_P_GNT1_N P3 24,29 IO_L85N_2_P3 PCI_P_GNT2_N R7 24,31 IO_L86P_2_R7 PCI_P_GNT3_N R8 24,33 IO_L86N_2_R8 PCI_P_GNT4_N P4 24,25 IO_L87P_2_P4 P5 SCH P/N 0381171-02 NC IO_L87N_2_P5 PCI_P_CLK0_R T2 ART P/N 0531311-02 7 IO_L88P_2_T2 PCI_P_CLK1_R R2 FAB P/N 1280333-02 7 IO_L88N_2/VREF_2_R2 PCI_P_CLK2_R R5 7 IO_L89P_2_R5 PCI_P_CLK3_R R6 7 IO_L89N_2_R6 PCI_P_CLK4_R R3 Title: ML310 VIRTEX-II PRO PLAFTORM 7 IO_L90P_2_R3 A PCI_P_CLK5_R R4 7 IO_L90N_2_R4 BANK2: PCI BUS, RESET, INTR A Date: 10-6-2003_14:59 Ver: X.X R435 Sheet Size: B Rev: X PCI_P_AD24 PCI_FPGA_IDSEL 7,25,27,29,31,33 7 Sheet 7 of 52 Drawn By 0 XXX 4 3 2 1 4 3 2 1 VCC2V5 XC2VP20-BANK3 FF896 R37 VRN_BANK3 (DIE DOWN) 8 U37 49.9 VRN_BANK3 AK3 8 IO_L01P_3/VRN_3_AK3 8 VRP_BANK3 AJ3 IO_L01N_3/VRP_3_AJ3 VCC2V5 D D R41 VRP_BANK3 PM_IO_0 AH5 T10 8 15,18 IO_L02P_3_AH5 VCCO_3_T10 PM_IO_1 AG5 U10 15,18 IO_L02N_3_AG5 VCCO_3_U10 49.9 15,18 PM_IO_2 AH2 IO_L03P_3_AH2 VCCO_3_Y9 Y9 PM_IO_3 AH1 V9 15,18 IO_L03N_3/VREF_3_AH1 VCCO_3_V9 PM_IO_4 AH4 W9 15,18 IO_L04P_3_AH4 VCCO_3_W9 PM_IO_5 AG3 W10 15,18 IO_L04N_3_AG3 VCCO_3_W10 AD6 V10 NC IO_L05P_3_AD6 VCCO_3_V10 AD5 Y10 NC IO_L05N_3_AD5 VCCO_3_Y10 PM_IO_6 AG2 AA9 15,18 IO_L06P_3_AG2 VCCO_3_AA9 PM_IO_7 AG1 AB9 15,18 IO_L06N_3_AG1 VCCO_3_AB9 PM_IO_8 AF6 15,18 IO_L31P_3_AF6 PM_IO_9 AE5 15,18 IO_L31N_3_AE5 AB8 NC IO_L32P_3_AB8 AB7 NC IO_L32N_3_AB7 PM_IO_10 AE4 15,18 IO_L33P_3_AE4 PM_IO_11 AE3 15,18 IO_L33N_3/VREF_3_AE3 PM_IO_12 AF4 15,18 IO_L34P_3_AF4 PM_IO_13 AF3 15,18 IO_L34N_3_AF3 AC6 NC IO_L35P_3_AC6 AC5 NC IO_L35N_3_AC5 PM_IO_14 AF2 15,18 IO_L36P_3_AF2 PM_IO_15 AF1 15,18 IO_L36N_3_AF1 PM_IO_16 AD4 15,18 IO_L37P_3_AD4 PM_IO_17 AD3 15,18 IO_L37N_3_AD3 AA8 NC IO_L38P_3_AA8 AA7 NC IO_L38N_3_AA7 C PM_IO_18 AE2 C 15,18 IO_L39P_3_AE2 PM_IO_19 AE1 15,18 IO_L39N_3/VREF_3_AE1 PM_IO_20 AB6 15,18 IO_L40P_3_AB6 PM_IO_21 AB5 15,18 IO_L40N_3_AB5 Y8 NC IO_L41P_3_Y8 Y7 NC IO_L41N_3_Y7 PM_IO_22 AD2 15,18 IO_L42P_3_AD2 PM_IO_23 AD1 15,18 IO_L42N_3_AD1 PM_IO_24 AC4 15,18 IO_L43P_3_AC4 PM_IO_25 AC3 15,18 IO_L43N_3_AC3 PM_IO_26 AA6 15,18 IO_L44P_3_AA6 PM_IO_27 AA5 15,18 IO_L44N_3_AA5 PM_IO_28 AC2 15,18 IO_L45P_3_AC2 PM_IO_29 AB2 15,18 IO_L45N_3/VREF_3_AB2 PM_IO_30 AB4 15,18 IO_L46P_3_AB4 PM_IO_31 AB3 15,18 IO_L46N_3_AB3 PM_IO_32 W8 15,18 IO_L47P_3_W8 PM_IO_33 W7 15,18 IO_L47N_3_W7 PM_IO_34 AA4 15,18 IO_L48P_3_AA4 PM_IO_35 AA3 15,18 IO_L48N_3_AA3 PM_IO_36 Y5 18 IO_L49P_3_Y5 PM_IO_37 Y4 18 IO_L49N_3_Y4 PM_IO_38 W6 18 IO_L50P_3_W6 PM_IO_39 W5 18 IO_L50N_3_W5 PM_IO_40 AB1 18 IO_L51P_3_AB1 PM_IO_41 AA1 18 IO_L51N_3/VREF_3_AA1 PM_IO_42 W4 18 IO_L52P_3_W4 PM_IO_43 W3 B 18 IO_L52N_3_W3 B PM_IO_44 V8 18 IO_L53P_3_V8 PM_IO_45 V7 18 IO_L53N_3_V7 PM_IO_46 AA2 18 IO_L54P_3_AA2 PM_IO_47 Y2 18 IO_L54N_3_Y2 PM_IO_48 V6 18 IO_L55P_3_V6 PM_IO_49 V5 18 IO_L55N_3_V5 PM_IO_50 U8 18 IO_L56P_3_U8 PM_IO_51 U7 18 IO_L56N_3_U7 PM_IO_52 Y1 18 IO_L57P_3_Y1 PM_IO_53 W1 18 IO_L57N_3/VREF_3_W1 PM_IO_54 V4 18 IO_L58P_3_V4 PM_IO_55 V3 18 IO_L58N_3_V3 PM_IO_56 U9 18 IO_L59P_3_U9 PM_IO_57 T9 18 IO_L59N_3_T9 PM_IO_58 W2 18 IO_L60P_3_W2 PM_IO_59 V2 18 IO_L60N_3_V2 PM_IO_60 U5 18 IO_L85P_3_U5 PM_IO_61 U4 18 IO_L85N_3_U4 PM_IO_62 T8 18 IO_L86P_3_T8 PM_IO_63 T7 18 IO_L86N_3_T7 PM_IO_64 U3 18 IO_L87P_3_U3 PM_IO_65 U2 SCH P/N 0381171-02 18 IO_L87N_3/VREF_3_U2 PM_IO_66 T4 ART P/N 0531311-02 18 IO_L88P_3_T4 PM_IO_67 T3 FAB P/N 1280333-02 18 IO_L88N_3_T3 PM_IO_68 T6 18 IO_L89P_3_T6 PM_IO_69 T5 18 IO_L89N_3_T5 PM_IO_70 V1 Title: ML310 VIRTEX-II PRO PLAFTORM 18 IO_L90P_3_V1 A PM_IO_71 U1 18 IO_L90N_3_U1 BANK3: PM LVDS IO A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 8 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 VCC2V5 XC2VP20-BANK4 R429 FF896 VRN_BANK4 9 (DIE DOWN) 49.9 U37 VRN_BANK4 AH8 9 IO_L06P_4/VRN_4_AH8 R432 9 VRP_BANK4 AG8 IO_L06N_4/VRP_4_AG8 VCC2V5 VRP_BANK4 D 9 D 49.9 9,19,20,46 FPGA_INIT AF7 IO_L01P_4/INIT_B_AF7 VCCO_4_AB10 AB10 AG6 AB11 NC IO_L01N_4/DOUT_AG6 VCCO_4_AB11 TRC_CLK_R AD9 AB12 9 IO_L02P_4/D1_AD9 VCCO_4_AB12 ATD_17 AC9 AB13 19 IO_L02N_4/D0_AC9 VCCO_4_AB13 TRC_TS1O AH7 AA10 19 IO_L03P_4/D3_AH7 VCCO_4_AA10 ATD_16 AG7 AA11 19 IO_L03N_4/D2_AG7 VCCO_4_AA11 TRC_TS2E AD8 AA12 19 IO_L05_4/No_Pair_AD8 VCCO_4_AA12 TRC_TS3 AD10 AA13 19 IO_L07P_4/VREF_4_AD10 VCCO_4_AA13 ATD_18 AC10 AA14 19 IO_L07N_4_AC10 VCCO_4_AA14 TRC_TS5 AE8 AA15 19 IO_L08P_4_AE8 VCCO_4_AA15 TRC_TS6 AE7 19 IO_L08N_4_AE7 NOTE: TRC_CLK RESISTOR ALLOWS CLOCK TERMINATION ATD_8 AK8 19 IO_L09P_4/VREF_4_AK8 ATD_9 AJ8 19 IO_L09N_4_AJ8 TO BE ADJUSTED INDEPENDENTLY OF OTHER I/O. ATD_15 AD11 19 IO_L37P_4_AD11 ATD_19 AC11 19 IO_L37N_4_AC11 ATD_13 AF9 19 IO_L38P_4_AF9 TRC_CLK R31 TRC_CLK_R 19 AATTDD__1120 AAG1F80 IO_L38N_4_AF8 19 9 19 IO_L39P_4_AG10 TRC_TS1E AF10 19 IO_L39N_4_AF10 24.9 19 TRC_TS2O AD12 IO_L43P_4_AD12 ATD_14 AC12 19 IO_L43N_4_AC12 ATD_11 AE10 19 IO_L44P_4_AE10 TRC_TS4 AE9 19 IO_L44N_4_AE9 CPU_TDI AJ9 19 IO_L45P_4/VREF_4_AJ9 CPU_TDO_TMP AH9 19 IO_L45N_4_AH9 CPU_TMS AD13 19 IO_L46P_4_AD13 C VCC2V5 19 CPU_TCK AC13 IO_L46N_4_AC13 C CPU_TRST_N AE12 19 IO_L47P_4_AE12 CPU_HALT_N AE11 R440 19 IO_L47N_4_AE11 FPGA_INIT AH11 9,19,20,46 NC IO_L48P_4_AH11 FPGA_LED_USER1 AH10 4.75K 47 IO_L48N_4_AH10 FPGA_LED_USER2 AC14 47 IO_L49P_4_AC14 OPB_BUS_ERROR AB14 46 IO_L49N_4_AB14 PLB_BUS_ERROR AF11 46 IO_L50_4/No_Pair_AF11 AG11 NC IO_L53_4/No_Pair_AG11 SPI_DATA_IN AK10 45 IO_L54P_4_AK10 SPI_DATA_OUT AJ10 45 IO_L54N_4_AJ10 SPI_DATA_CS_N AF13 45 SPI_CLK AF12 IO_L56P_4_AF13 45 IO_L56N_4_AF12 AH13 NC IO_L57P_4/VREF_4_AH13 AG13 NC IO_L57N_4_AG13 PM_IO_72 AC15 15,18 IO_L67P_4_AC15 PM_IO_73 AB15 15,18 IO_L67N_4_AB15 PM_IO_74 AE14 15,18 IO_L68P_4_AE14 PM_IO_75 AD14 15,18 IO_L68N_4_AD14 PM_IO_76 AG14 15,18 IO_L69P_4/VREF_4_AG14 PM_IO_77 AF14 15,18 IO_L69N_4_AF14 AE15 NC IO_L73P_4_AE15 AD15 NC IO_L73N_4_AD15 LVDS_CLKEXT_P AJ15 6,9,18 IO_L75P_4/GCLK0P_AJ15 VCC2V5 6,9,18 LVDS_CLKEXT_N AH15 IO_L75N_4/GCLK1S_AH15 PM_CLK_BOT AG15 B 18 IO_L74P_4/GCLK2P_AG15 B SYSACE_FPGA_CLK AF15 9 IO_L74N_4/GCLK3S_AF15 R421 4.75K LVDS_CLKEXT_P R422 6,9,18 SYSACE_CLK_OE 5 0 R414 LVDS_CLKEXT_N 6,9,18 100 VCC2V5 VCC2V5 X8 1 4 OE VCC R411 C542 SYSACE_FPGA_CLK OSC 9 0.1UF SCH P/N 0381171-02 34.0 ART P/N 0531311-02 R412 2 3 SYSACE_CLK_OSC SYSACE_CLK_R FAB P/N 1280333-02 GND OUT 18.2 SG-636PDE R410 33.0000MHZ SYSACE_CLK Title: ML310 VIRTEX-II PRO PLAFTORM 20 A 34.0 BANK4: TRACE, CPU DEBUG, PM I/O A Date: 1-5-2004_13:05 Ver: X.X Sheet Size: B Rev: X Sheet 9 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK5 VCC2V5 FF896 R386 10,11,12,21,23 VREF_DDR (DIE DOWN) VRN_BANK5 U37 10 49.9 10 VRN_BANK5 AG23 IO_L06P_5/VRN_5_AG23 10 VRP_BANK5 AH23 IO_L06N_5/VRP_5_AH23 VCC2V5 D D R375 10 DDR_CLK_FB AG25 IO_L01P_5/CS_B_AG25 VCCO_5_AB18 AB18 VRP_BANK5 AF24 AB19 10 NC IO_L01N_5/RDWR_B_AF24 VCCO_5_AB19 AC22 AB20 NC IO_L02P_5/D7_AC22 VCCO_5_AB20 49.9 NC AD22 IO_L02N_5/D6_AD22 VCCO_5_AB21 AB21 DDR_CKE0 AG24 AA16 21,22 IO_L03P_5/D5_AG24 VCCO_5_AA16 DDR_CKE1 AH24 AA17 21,22 IO_L03N_5/D4_AH24 VCCO_5_AA17 AD23 AA18 NC IO_L05_5/No_Pair_AD23 VCCO_5_AA18 AC21 AA19 NC IO_L07P_5_AC21 VCCO_5_AA19 AD21 AA20 IO_L07N_5/VREF_5_AD21 VCCO_5_AA20 AE24 AA21 NC IO_L08P_5_AE24 VCCO_5_AA21 DDR_A12 AE23 21,22 IO_L08N_5_AE23 DDR_A11 AJ23 21,22 IO_L09P_5_AJ23 AK23 IO_L09N_5/VREF_5_AK23 AC20 NC IO_L37P_5_AC20 AD20 NC IO_L37N_5_AD20 DDR_A09 AF23 21,22 IO_L38P_5_AF23 DDR_A07 AF22 21,22 IO_L38N_5_AF22 DDR_A06 AF21 21,22 DDR_A04 AG21 IO_L39P_5_AF21 21,22 IO_L39N_5_AG21 AC19 NC IO_L43P_5_AC19 AD19 NC IO_L43N_5_AD19 AE22 NC IO_L44P_5_AE22 VREF_DDR AE21 10,11,12,21,23 NC IO_L44N_5_AE21 DDR_A08 AH22 21,22 IO_L45P_5_AH22 AJ22 IO_L45N_5/VREF_5_AJ22 C157 C156 AC18 NC IO_L46P_5_AC18 C 0.1UF 0.01UF AD18 C NC IO_L46N_5_AD18 AE20 NC IO_L47P_5_AE20 AE19 DDR_A05 NC AH21 IO_L47N_5_AE19 21,22 DDR_A01 AH20 IO_L48P_5_AH21 21,22 IO_L48N_5_AH20 AB17 NC IO_L49P_5_AB17 AC17 NC IO_L49N_5_AC17 DDR_A00 AF20 21,22 DDR_A10 AG20 IO_L50_5/No_Pair_AF20 21,22 IO_L53_5/No_Pair_AG20 DDR_A03 AJ21 21,22 IO_L54P_5_AJ21 DDR_A02 AK21 21,22 DDR_BA0 AF19 IO_L54N_5_AK21 21,22 DDR_S1_N AF18 IO_L56P_5_AF19 21,22 DDR_BA1 AG18 IO_L56N_5_AF18 21,22 IO_L57P_5_AG18 AH18 IO_L57N_5/VREF_5_AH18 AB16 NC IO_L67P_5_AB16 AC16 NC IO_L67N_5_AC16 AD17 DDR_S0_N NC AE17 IO_L68P_5_AD17 21,22 DDR_CAS_N AF17 IO_L68N_5_AE17 21,22 IO_L69P_5_AF17 AG17 DDR_WE_N AD16 IO_L69N_5/VREF_5_AG17 21,22 DDR_RAS_N AE16 IO_L73P_5_AD16 21,22 IO_L73N_5_AE16 DDR_CLK_FB AF16 10 IO_L74P_5/GCLK4P_AF16 USER_CLKSYS AG16 10 IO_L74N_5/GCLK5S_AG16 LVDS_CLKLOC_P AH16 B 5,10 IO_L75P_5/GCLK6P_AH16 B VCC2V5 5,10 LVDS_CLKLOC_N AJ16 IO_L75N_5/GCLK7S_AJ16 R367 X6 1 14 OE1 VCC1 LVDS_CLKLOC_P 4.75K 5,10 OSC R408 C446 4 11 LVDS_CLKLOC_N OE2 VCC2 5,10 0.1UF 100 R366 7 8 USER_CLKSYS_R USER_CLKSYS GND OUT 10 24.9 MB2100H 100.0000MHZ NOSTUFF XS6 SOCKETED 14-PIN DIP SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A BANK5: DDR A Date: 12-2-2003_13:35 Ver: X.X Sheet Size: B Rev: X Sheet 10 of 52 Drawn By XXX 4 3 2 1

Description:
PCB FABRICATION. SCHEMATICS. XILINX PART NUMBERS. 0381171-02. 0531311-02. 1280333-02. NOSTUFF ITEMS ARE NOT POPULATED ON
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pcb artwork pcb fabrication schematics xilinx part numbers 0381171-02 0531311-02 1280333-02 PDF

52 Pages·2004·6.54 MB·English
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Preview pcb artwork pcb fabrication schematics xilinx part numbers 0381171-02 0531311-02 1280333-02

4 3 2 1 D D PAGE 1: TABLE OF CONTENTS PAGE 2: <<BLANK>> PAGE 3: <<BLANK>> PAGE 4: <<BLANK>> PAGE 5: BANK0: SYSACE, LCD, SPI PAGE 6: BANK1: PM I/O, UART, DEBUG LED, I2C PAGE 7: BANK2: PCI BUS, RESET, INTR PAGE 8: BANK3: PM LVDS IO PAGE 9: BANK4: TRACE, CPU DEBUG, PM I/O NOTE: PLEASE REVIEW THE ML310 BOM FOR ITEMS DESIGNATED AS "NOSTUFF". PAGE 10: BANK5: DDR PAGE 11: BANK6: DDR NOSTUFF ITEMS ARE NOT POPULATED ON THE PCB. C PAGE 12: BANK7: DDR C PAGE 13: FPGA CONFIG AND MISC I/O THE ML310 BOM CONTAINS THE MOST ACCURATE INFORMATION ABOUT PAGE 14: FPGA DECOUPLING PAGE 15: MGT POWER SUPPLIES NOSTUFF DISCRETES AND COMPONENTS. PAGE 16: TOP MGT TRANSCEIVERS PAGE 17: BOT MGT TRANSCEIVERS PAGE 18: PERSONALITY MODULE CONNECTORS PAGE 19: JTAG, DEBUG, TRACE CONNECTORS PAGE 20: SYSTEM ACE AND COMPACT FLASH PAGE 21: DDR DIMM CONNECTOR PAGE 22: DDR SSTL-2 TERMINATION PAGE 23: DDR TERMINATION SUPPLY XILINX PART NUMBERS PAGE 24: PCI BUS PULLUPS PAGE 25: PCI-PCI BRIDGE PAGE 26: PCI SLOT 6, 5.0V, SECONDARY BUS PAGE 27: PCI SLOT 5, 3.3V, PRIMARY BUS PAGE 28: PCI SLOT 4, 5.0V, SECONDARY BUS SCHEMATICS 0381171-02 PAGE 29: PCI SLOT 3, 3.3V, PRIMARY BUS PAGE 30: << BLANK >> B B PCB ARTWORK 0531311-02 PAGE 31: PCI ETHERNET MAC/PHY PAGE 32: PCI ETHERNET INTERFACE, PROM PAGE 33: PCI SOUTH BRIDGE, PART 1 PCB FABRICATION 1280333-02 PAGE 34: PCI SOUTH BRIDGE, PART 2-3 PAGE 35: PCI SOUTH BRIDGE, PART 4-5 PAGE 36: PCI SOUTH BRIDGE, CONFIG RESISTORS PAGE 37: PCI SOUTH BRIDGE, UNUSED PIN RESISTORS PAGE 38: PARALLEL PORT INTERFACE PAGE 39: RS232 SERIAL PORT INTERFACE PAGE 40: KBD/MOUSE AND USB INTERFACES PAGE 41: IDE INTERFACES PAGE 42: SOUTH BRIDGE ROM AND GPIO PAGE 43: AC97 CODEC PAGE 44: AC97 CONNECTORS SCH P/N 0381171-02 PAGE 45: I2C AND SPI DEVICES ART P/N 0531311-02 PAGE 46: DEBUG AND STATUS LEDS FAB P/N 1280333-02 PAGE 47: ATX AND FRONT PANEL CONNECTORS PAGE 48: RESET SWITCHES AND FPGA SERIAL PORT Title: ML310 VIRTEX-II PRO PLAFTORM A PAGE 49: ATX CONNECTOR AND DC-DC CONVERTORS TABLE OF CONTENTS PAGE 50: POWER SUPPLY MONITORS AND LEDS A PAGE 51: ATX MOUNTING HOLES AND TEST POINTS Date: 6-4-2004_12:54 Ver: X.X PAGE 52: FPGA FAN SWITCH AND TACH Sheet Size: B Rev: X Sheet 1 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 2 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 3 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 D D C C B B SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A <<INSERT SHEET NAME HERE>> A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 4 of 51 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK0 VCC2V5 FF896 R374 (DIE DOWN) VRN_BANK0 U37 5 49.9 5 VRN_BANK0 E24 IO_L01P_0/VRN_0_E24 5 VRP_BANK0 E25 IO_L01N_0/VRP_0_E25 VCC2V5 D D R385 VRP_BANK0 SYSACE_MPIRQ F23 J18 5 20 IO_L02P_0_F23 VCCO_0_J18 SYSACE_MPBRDY F24 J19 20 IO_L02N_0_F24 VCCO_0_J19 49.9 20 SYSACE_MPCE E22 IO_L03P_0/VREF_0_E22 VCCO_0_J20 J20 SYSACE_MPOE E23 J21 20 IO_L03N_0_E23 VCCO_0_J21 SYSACE_MPWE G23 K16 20 IO_L05_0/No_Pair_G23 VCCO_0_K16 SYSACE_MPD15 G22 K17 20 IO_L06P_0_G22 VCCO_0_K17 SYSACE_MPD14 H22 K18 20 IO_L06N_0_H22 VCCO_0_K18 SYSACE_MPD13 F21 K19 20 IO_L07P_0_F21 VCCO_0_K19 VCC2V5 20 SYSACE_MPD12 F22 IO_L07N_0_F22 VCCO_0_K20 K20 SYSACE_MPD11 C24 K21 20 IO_L08P_0_C24 VCCO_0_K21 SYSACE_MPD10 D24 20 IO_L08N_0_D24 SYSACE_MPD09 G21 20 IO_L09P_0/VREF_0_G21 SYSACE_MPD08 H21 2 J17 R28 80.6 222000 SSYYSSAACCEE__MMPPDD0067 ED2211 IIIOOO___LLL033977NNP___000___HED222111 SYSACE_MPD05 C23 20 IO_L38P_0_C23 3 SYSACE_MPD04 D23 20 IO_L38N_0_D23 1 USER_SMA_CLK SYSACE_MPD03 G20 5 20 IO_L39P_0_G20 4 SYSACE_MPD02 H20 20 IO_L39N_0_H20 SYSACE_MPD01 D20 CO5N_SMA_ST R407 130 222000 SSYYSSAACCEE__MMPPAD0060 EA2203 IIIOOO___LLL444334NPP___000___EDA222003 SYSACE_MPA05 B23 20 IO_L44N_0_B23 SYSACE_MPA04 G19 20 IO_L45P_0/VREF_0_G19 SYSACE_MPA03 H19 20 IO_L45N_0_H19 SYSACE_MPA02 E18 20 IO_L46P_0_E18 C SYSACE_MPA01 E19 C 20 IO_L46N_0_E19 SYSACE_MPA00 B22 20 IO_L47P_0_B22 SYSACE_CLK_OE C22 9 IO_L47N_0_C22 FPGA_LCD_DB0 F19 47 IO_L48P_0_F19 FPGA_LCD_DB1 F20 47 IO_L48N_0_F20 FPGA_LCD_DB2 F17 47 IO_L49P_0_F17 FPGA_LCD_DB3 G17 47 IO_L49N_0_G17 FPGA_LCD_DB4 B21 47 IO_L50_0/No_Pair_B21 FPGA_LCD_DB5 A21 47 IO_L53_0/No_Pair_A21 FPGA_LCD_DB6 G18 47 IO_L54P_0_G18 FPGA_LCD_DB7 H18 47 IO_L54N_0_H18 FPGA_LCD_DIR C20 47 IO_L56P_0_C20 FPGA_LCD_E C21 46 IO_L56N_0_C21 FPGA_LCD_RW H17 46 IO_L57P_0/VREF_0_H17 NOTE: 130 OHM RESISTORS ON EG-2121 OUTPUTS ARE FPGA_LCD_RS J17 46 IO_L57N_0_J17 PM_IO_78 D17 18 IO_L67P_0_D17 INTENDED TO PROVIDE A LOAD FOR THE PECL PM_IO_79 E17 18 IO_L67N_0_E17 PM_IO_80 C18 18 IO_L68P_0_C18 DRIVERS AND SHOULD BE PLACED NEAR THE OSC. PM_IO_81 D18 18 IO_L68N_0_D18 PM_IO_82 H16 18 IO_L69P_0/VREF_0_H16 PM_IO_83 J16 18 IO_L69N_0_J16 VCC2V5 NC D16 IO_L73P_0_D16 FPGA_CPU_RESET_N E16 48 IO_L73N_0_E16 FB5 R400 X7 1 6 LVDS_CLKLOC_P F16 OE VCC 5,10 IO_L75P_0/GCLK4S_F16 BLM18AG LVDS_CLKLOC_N G16 4.75K 5,10 IO_L75N_0/GCLK5P_G16 PM_CLK_TOP B16 B 18 IO_L74P_0/GCLK6S_B16 B C193 C194 C184 2 5 LVDS_CLKLOC1_N USER_SMA_CLK C16 NC OSC N 5 IO_L74N_0/GCLK7P_C16 0.1UF 0.1UF 10UF 6.3V 3 4 LVDS_CLKLOC1_P GND P EG-2121CA NOTE: IN ORDER TO FACILITATE TEST POINT INSERTION FOR 156.2500MHZ R402 130 R401 130 1 BGA PACKAGE DEVICES, THE UNUSED PINS ON THE BGAS 2 LVDS_CLKLOC_P 5,10 ARE TIED TO AN "UNUSED PIN" NET EVEN THOUGH THEY 3 APPEAR TO BE NO-CONNECTS IN THE SCHEMATIC. PLEASE J20 CHECK THE NETLISTS BEFORE MODIFYING ANY NC PINS ON 1 A BGA PACKAGE TO ENSURE THE LAYOUT AND SCHEMATIC VCC2V5 2 LVDS_CLKLOC_N REMAIN CONSISTENT. 5,10 FB16 R417 X9 3 1 6 OE VCC BLM18AG 4.75K J21 SCH P/N 0381171-02 ART P/N 0531311-02 C212 C213 C207 2 5 LVDS_CLKLOC2_N FAB P/N 1280333-02 NC OSC N 0.1UF 0.1UF 10UF 6.3V 3 4 LVDS_CLKLOC2_P Title: ML310 VIRTEX-II PRO PLAFTORM GND P A EG-2121CA BANK0: SYSACE, LCD, SPI 125.0000MHZ R419 130 R418 130 A Date: 6-4-2004_12:58 Ver: X.X Sheet Size: B Rev: X Sheet 5 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK1 FF896 (DIE DOWN) VCC3_PCI U37 VRN_BANK1 E6 6 IO_L01P_1/VRN_1_E6 R431 6 VRP_BANK1 E7 IO_L01N_1/VRP_1_E7 VCC3_PCI VRN_BANK1 D 6 D 49.9 18 PM_IO_3V_0 F7 IO_L02P_1_F7 VCCO_1_J10 J10 PM_IO_3V_1 F8 J11 18 IO_L02N_1_F8 VCCO_1_J11 PM_IO_3V_2 E8 J12 18 IO_L03P_1_E8 VCCO_1_J12 R428 18 PM_IO_3V_3 E9 IO_L03N_1/VREF_1_E9 VCCO_1_J13 J13 VRP_BANK1 G8 K10 6 NC IO_L05_1/No_Pair_G8 VCCO_1_K10 PM_IO_3V_4 H9 K11 18 IO_L06P_1_H9 VCCO_1_K11 49.9 18 PM_IO_3V_5 G9 IO_L06N_1_G9 VCCO_1_K12 K12 PM_IO_3V_6 F9 K13 18 IO_L07P_1_F9 VCCO_1_K13 PM_IO_3V_7 F10 K14 18 IO_L07N_1_F10 VCCO_1_K14 PM_IO_3V_8 D7 K15 18 IO_L08P_1_D7 VCCO_1_K15 PM_IO_3V_9 C7 18 IO_L08N_1_C7 PM_IO_3V_10 H10 18 IO_L09P_1_H10 PM_IO_3V_11 G10 18 IO_L09N_1/VREF_1_G10 PM_IO_3V_12 E10 18 IO_L37P_1_E10 PM_IO_3V_13 D10 18 IO_L37N_1_D10 VCC5V 18 PM_IO_3V_14 D8 IO_L38P_1_D8 VCC3_PCI 18 PM_IO_3V_15 C8 IO_L38N_1_C8 PM_IO_3V_16 H11 18 IO_L39P_1_H11 U41 PM_IO_3V_17 G11 18 IO_L39N_1_G11 8 1 PM_IO_3V_18 E11 IN OUT 18 IO_L43P_1_E11 PM_IO_3V_19 D11 18 IO_L43N_1_D11 5 SHDN GND33 18 PM_IO_3V_20 B8 IO_L44P_1_B8 C236 PM_IO_3V_21 A8 1 18 IO_L44N_1_A8 C 2120UVF NC 42 BYPADJ GGNNDD6776 R455 38.3 1206 2 C362..3337UVF 11118888 PPPPMMMM____IIIIOOOO____3333VVVV____22222345 EEGH11113222 IIIIOOOO____LLLL44446655NPNP____1111__/_EEVH11R132E2F_1_G12 C LT1763CS8 C9 NC IO_L47P_1_C9 JTAG_SRC_SEL B9 19 IO_L47N_1_B9 F11 NC IO_L48P_1_F11 UART0_TXD F12 48 IO_L48N_1_F12 UART0_RTS_N G14 R454 26.1 1206 444888 UUAARRTT00__CRTXSD_N NC ABF111004 IIIIOOOO____LLLL55443099__NP11__//11NN__ooFG__11PP44aaiirr__AB1100 DBG_LED_0 H13 46 IO_L54P_1_H13 DBG_LED_1 G13 46 IO_L54N_1_G13 DBG_LED_2 C10 46 IO_L56P_1_C10 DBG_LED_3 C11 46 IO_L56N_1_C11 DBG_LED_4 J14 46 IO_L57P_1_J14 NOTE: THE COMPONENT VALUES FOR THIS REGULATOR ARE TAKEN DBG_LED_5 H14 46 IO_L57N_1/VREF_1_H14 DBG_LED_6 E14 46 IO_L67P_1_E14 FROM XAPP653. THIS DESIGN IS INTENDED TO SINK CURRENT DBG_LED_7 D14 46 IO_L67N_1_D14 D13 NC IO_L68P_1_D13 THROUGH THE 1206 RESISTORS WHEN THE CLAMP DIODES ON FPGA_SCL C13 6 IO_L68N_1_C13 FPGA_SDA J15 6 IO_L69P_1_J15 THE FPGA ARE CONDUCTING DURING OVERSHOOT. THIS IS WHY IIC_ALERT_N H15 35,45 IO_L69N_1/VREF_1_H15 IIC_IRQ_N E15 THE VALUES ARE UNUSUAL RELATIVE TO THE LT1763 DATASHEET. 45 IIC_THERM_N D15 IO_L73P_1_E15 35,45 IO_L73N_1_D15 PCI_P_CLK5 C15 7 IO_L74P_1/GCLK0S_C15 USER_CLKPCI B15 6 IO_L74N_1/GCLK1P_B15 LVDS_CLKEXT_P G15 B 9,18 IO_L75P_1/GCLK2S_G15 B LVDS_CLKEXT_N F15 R426 9,18 IO_L75N_1/GCLK3P_F15 IIC_SCL FPGA_SCL 21,35,45 6 0 R427 IIC_SDA FPGA_SDA 21,35,45 6 0 VCC3V3 R448 X10 1 14 OE1 VCC1 4.75K OSC C581 0.1UF 4 11 OE2 VCC2 SCH P/N 0381171-02 ART P/N 0531311-02 R447 7 8 USER_CLKPCI_R USER_CLKPCI FAB P/N 1280333-02 GND OUT 6 24.9 SG-531PCW 33.0000MHZ Title: ML310 VIRTEX-II PRO PLAFTORM A NOSTUFF NOTE: X10 IS REPLACED WITH A 100MHZ 3.3V OSCILLATOR BANK1: PM I/O, UART, DEBUG LED, I2C XS10 AND IS USED AS THE PRIMARY FPGA REFCLK INPUT ON A SOCKETED Date: 1-5-2004_13:05 Ver: X.X 14-PIN DIP PRODUCTION BOARDS AS A LOWER COST ALTERNATIVE TO Sheet Size: B Rev: X USING A 100MHZ 2.5V OSCILLATOR IN LOCATION X6. Sheet 6 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK2 FF896 (DIE DOWN) VCC3_PCI U37 VRN_BANK2 B3 7 IO_L01P_2/VRN_2_B3 R38 7 VRP_BANK2 A3 IO_L01N_2/VRP_2_A3 VCC3_PCI VRN_BANK2 D 7 R2 D PCI_P_CLK0 7,27 49.9 25,27,29,31,33 PCI_P_AD00 G5 IO_L02P_2_G5 VCCO_2_J9 J9 4.75K PCI_P_AD01 G6 K9 25,27,29,31,33 IO_L02N_2_G6 VCCO_2_K9 PCI_P_AD02 D5 L9 25,27,29,31,33 IO_L03P_2_D5 VCCO_2_L9 R1 R35 25,27,29,31,33 PCI_P_AD03 C5 IO_L03N_2_C5 VCCO_2_L10 L10 7,29 PCI_P_CLK1 VRP_BANK2 PCI_P_AD04 C1 M9 7 25,27,29,31,33 IO_L04P_2_C1 VCCO_2_M9 4.75K PCI_P_AD05 C2 M10 25,27,29,31,33 IO_L04N_2/VREF_2_C2 VCCO_2_M10 49.9 25,27,29,31,33 PCI_P_AD06 J7 IO_L05P_2_J7 VCCO_2_N9 N9 R200 PCI_P_AD07 J8 N10 PCI_P_CLK2 25,27,29,31,33 IO_L05N_2_J8 VCCO_2_N10 7,31 PCI_P_AD08 D3 P10 25,27,29,31,33 IO_L06P_2_D3 VCCO_2_P10 4.75K PCI_P_AD09 C4 R10 25,27,29,31,33 IO_L06N_2_C4 VCCO_2_R10 PCI_P_AD10 D1 25,27,29,31,33 IO_L31P_2_D1 R164 PCI_P_AD11 D2 PCI_P_CLK3 25,27,29,31,33 IO_L31N_2_D2 7,33 PCI_P_AD12 H5 25,27,29,31,33 IO_L32P_2_H5 4.75K PCI_P_AD13 H6 25,27,29,31,33 IO_L32N_2_H6 PCI_P_AD14 E3 25,27,29,31,33 IO_L33P_2_E3 R382 PCI_P_AD15 E4 PCI_P_CLK4 25,27,29,31,33 IO_L33N_2_E4 7,25 PCI_P_AD16 E1 25,27,29,31,33 IO_L34P_2_E1 4.75K PCI_P_AD17 E2 25,27,29,31,33 IO_L34N_2/VREF_2_E2 PCI_P_AD18 K7 25,27,29,31,33 IO_L35P_2_K7 R439 PCI_P_AD19 K8 PCI_P_CLK5 25,27,29,31,33 IO_L35N_2_K8 6,7 PCI_P_AD20 F3 25,27,29,31,33 IO_L36P_2_F3 4.75K PCI_P_AD21 F4 25,27,29,31,33 IO_L36N_2_F4 PCI_P_AD22 F1 25,27,29,31,33 IO_L37P_2_F1 PCI_P_AD23 F2 25,27,29,31,33 IO_L37N_2_F2 PCI_P_AD24 J5 7,25,27,29,31,33 IO_L38P_2_J5 PCI_P_AD25 J6 25,27,29,31,33 IO_L38N_2_J6 C PCI_P_AD26 G3 C 25,27,29,31,33 IO_L39P_2_G3 PCI_P_AD27 G4 NOTE: THE PCI SPEC RECOMMENDS THAT 25,27,29,31,33 IO_L39N_2_G4 PCI_P_AD28 G1 25,27,29,31,33 IO_L40P_2_G1 PCI_P_AD29 G2 CLOCKS BE PULLED LOW WHEN THE 25,27,29,31,33 IO_L40N_2/VREF_2_G2 PCI_P_AD30 L7 25,27,29,31,33 IO_L41P_2_L7 PCI_P_AD31 L8 BUS IS NOT ACTIVELY CLOCKED. 25,27,29,31,33 IO_L41N_2_L8 PCI_P_PAR H3 25,27,29,31,33 IO_L42P_2_H3 H4 NC IO_L42N_2_H4 PCI_P_CBE0_N J2 25,27,29,31,33 IO_L43P_2_J2 PCI_P_CBE1_N H2 25,27,29,31,33 IO_L43N_2_H2 PCI_P_CBE2_N M7 25,27,29,31,33 IO_L44P_2_M7 PCI_P_CBE3_N M8 NOTE: PCI_CLK RESISTORS ALLOW CLOCK TERMINATION 25,27,29,31,33 IO_L44N_2_M8 K5 NC IO_L45P_2_K5 PCI_P_FRAME_N K6 TO BE ADJUSTED INDEPENDENTLY OF OTHER I/O. 24,25,27,29,31,33 IO_L45N_2_K6 PCI_P_IRDY_N K1 24,25,27,29,31,33 IO_L46P_2_K1 PCI_P_TRDY_N J1 24,25,27,29,31,33 IO_L46N_2/VREF_2_J1 PCI_P_STOP_N M5 24,25,27,29,31,33 IO_L47P_2_M5 PCI_P_DEVSEL_N M6 24,25,27,29,31,33 IO_L47N_2_M6 R50 PCI_P_PERR_N J3 PCI_P_CLK0_R PCI_P_CLK0 24,25,27,29,31 IO_L48P_2_J3 7 7,27 PCI_P_SERR_N J4 24,25,27,29,31,33 IO_L48N_2_J4 24.9 PCI_P_LOCK_N L2 24,25,27,29 IO_L49P_2_L2 PCI_FPGA_IDSEL K2 7 IO_L49N_2_K2 R49 N7 PCI_P_CLK1_R PCI_P_CLK1 NC IO_L50P_2_N7 7 7,29 PCI_P_RST_N N8 24,25,27,29,31 IO_L50N_2_N8 24.9 IIC_RESET_N K3 45 IO_L51P_2_K3 SBR_PWG K4 33 IO_L51N_2_K4 R436 SBR_RSM_RSTJ M1 PCI_P_CLK2_R PCI_P_CLK2 35 IO_L52P_2_M1 7 7,31 SBR_IDE_RST_N L1 B 41 IO_L52N_2/VREF_2_L1 24.9 B N5 NC IO_L53P_2_N5 SBR_INTR N6 33 IO_L53N_2_N6 R434 SBR_NMI L4 PCI_P_CLK3_R PCI_P_CLK3 33 IO_L54P_2_L4 7 7,33 PCI_P_INTA_N L5 24,27,29,33 IO_L54N_2_L5 24.9 PCI_P_INTB_N N2 24,27,29,33 IO_L55P_2_N2 PCI_P_INTC_N M2 24,27,29,31,33 IO_L55N_2_M2 R438 PCI_P_INTD_N R9 PCI_P_CLK4_R PCI_P_CLK4 24,27,29,33 IO_L56P_2_R9 7 7,25 PCI_S_INTA_N P9 24,26,28,33 IO_L56N_2_P9 24.9 PCI_S_INTB_N M3 24,26,28,33 IO_L57P_2_M3 M4 NC IO_L57N_2_M4 R437 PCI_P_REQ0_N P1 PCI_P_CLK5_R PCI_P_CLK5 24,27 IO_L58P_2_P1 7 6,7 PCI_P_REQ1_N N1 24,29 IO_L58N_2/VREF_2_N1 24.9 PCI_P_REQ2_N P7 24,31 IO_L59P_2_P7 PCI_P_REQ3_N P8 24,33,36 IO_L59N_2_P8 PCI_P_REQ4_N N3 24,25 IO_L60P_2_N3 N4 NC IO_L60N_2_N4 PCI_P_GNT0_N P2 24,27 IO_L85P_2_P2 PCI_P_GNT1_N P3 24,29 IO_L85N_2_P3 PCI_P_GNT2_N R7 24,31 IO_L86P_2_R7 PCI_P_GNT3_N R8 24,33 IO_L86N_2_R8 PCI_P_GNT4_N P4 24,25 IO_L87P_2_P4 P5 SCH P/N 0381171-02 NC IO_L87N_2_P5 PCI_P_CLK0_R T2 ART P/N 0531311-02 7 IO_L88P_2_T2 PCI_P_CLK1_R R2 FAB P/N 1280333-02 7 IO_L88N_2/VREF_2_R2 PCI_P_CLK2_R R5 7 IO_L89P_2_R5 PCI_P_CLK3_R R6 7 IO_L89N_2_R6 PCI_P_CLK4_R R3 Title: ML310 VIRTEX-II PRO PLAFTORM 7 IO_L90P_2_R3 A PCI_P_CLK5_R R4 7 IO_L90N_2_R4 BANK2: PCI BUS, RESET, INTR A Date: 10-6-2003_14:59 Ver: X.X R435 Sheet Size: B Rev: X PCI_P_AD24 PCI_FPGA_IDSEL 7,25,27,29,31,33 7 Sheet 7 of 52 Drawn By 0 XXX 4 3 2 1 4 3 2 1 VCC2V5 XC2VP20-BANK3 FF896 R37 VRN_BANK3 (DIE DOWN) 8 U37 49.9 VRN_BANK3 AK3 8 IO_L01P_3/VRN_3_AK3 8 VRP_BANK3 AJ3 IO_L01N_3/VRP_3_AJ3 VCC2V5 D D R41 VRP_BANK3 PM_IO_0 AH5 T10 8 15,18 IO_L02P_3_AH5 VCCO_3_T10 PM_IO_1 AG5 U10 15,18 IO_L02N_3_AG5 VCCO_3_U10 49.9 15,18 PM_IO_2 AH2 IO_L03P_3_AH2 VCCO_3_Y9 Y9 PM_IO_3 AH1 V9 15,18 IO_L03N_3/VREF_3_AH1 VCCO_3_V9 PM_IO_4 AH4 W9 15,18 IO_L04P_3_AH4 VCCO_3_W9 PM_IO_5 AG3 W10 15,18 IO_L04N_3_AG3 VCCO_3_W10 AD6 V10 NC IO_L05P_3_AD6 VCCO_3_V10 AD5 Y10 NC IO_L05N_3_AD5 VCCO_3_Y10 PM_IO_6 AG2 AA9 15,18 IO_L06P_3_AG2 VCCO_3_AA9 PM_IO_7 AG1 AB9 15,18 IO_L06N_3_AG1 VCCO_3_AB9 PM_IO_8 AF6 15,18 IO_L31P_3_AF6 PM_IO_9 AE5 15,18 IO_L31N_3_AE5 AB8 NC IO_L32P_3_AB8 AB7 NC IO_L32N_3_AB7 PM_IO_10 AE4 15,18 IO_L33P_3_AE4 PM_IO_11 AE3 15,18 IO_L33N_3/VREF_3_AE3 PM_IO_12 AF4 15,18 IO_L34P_3_AF4 PM_IO_13 AF3 15,18 IO_L34N_3_AF3 AC6 NC IO_L35P_3_AC6 AC5 NC IO_L35N_3_AC5 PM_IO_14 AF2 15,18 IO_L36P_3_AF2 PM_IO_15 AF1 15,18 IO_L36N_3_AF1 PM_IO_16 AD4 15,18 IO_L37P_3_AD4 PM_IO_17 AD3 15,18 IO_L37N_3_AD3 AA8 NC IO_L38P_3_AA8 AA7 NC IO_L38N_3_AA7 C PM_IO_18 AE2 C 15,18 IO_L39P_3_AE2 PM_IO_19 AE1 15,18 IO_L39N_3/VREF_3_AE1 PM_IO_20 AB6 15,18 IO_L40P_3_AB6 PM_IO_21 AB5 15,18 IO_L40N_3_AB5 Y8 NC IO_L41P_3_Y8 Y7 NC IO_L41N_3_Y7 PM_IO_22 AD2 15,18 IO_L42P_3_AD2 PM_IO_23 AD1 15,18 IO_L42N_3_AD1 PM_IO_24 AC4 15,18 IO_L43P_3_AC4 PM_IO_25 AC3 15,18 IO_L43N_3_AC3 PM_IO_26 AA6 15,18 IO_L44P_3_AA6 PM_IO_27 AA5 15,18 IO_L44N_3_AA5 PM_IO_28 AC2 15,18 IO_L45P_3_AC2 PM_IO_29 AB2 15,18 IO_L45N_3/VREF_3_AB2 PM_IO_30 AB4 15,18 IO_L46P_3_AB4 PM_IO_31 AB3 15,18 IO_L46N_3_AB3 PM_IO_32 W8 15,18 IO_L47P_3_W8 PM_IO_33 W7 15,18 IO_L47N_3_W7 PM_IO_34 AA4 15,18 IO_L48P_3_AA4 PM_IO_35 AA3 15,18 IO_L48N_3_AA3 PM_IO_36 Y5 18 IO_L49P_3_Y5 PM_IO_37 Y4 18 IO_L49N_3_Y4 PM_IO_38 W6 18 IO_L50P_3_W6 PM_IO_39 W5 18 IO_L50N_3_W5 PM_IO_40 AB1 18 IO_L51P_3_AB1 PM_IO_41 AA1 18 IO_L51N_3/VREF_3_AA1 PM_IO_42 W4 18 IO_L52P_3_W4 PM_IO_43 W3 B 18 IO_L52N_3_W3 B PM_IO_44 V8 18 IO_L53P_3_V8 PM_IO_45 V7 18 IO_L53N_3_V7 PM_IO_46 AA2 18 IO_L54P_3_AA2 PM_IO_47 Y2 18 IO_L54N_3_Y2 PM_IO_48 V6 18 IO_L55P_3_V6 PM_IO_49 V5 18 IO_L55N_3_V5 PM_IO_50 U8 18 IO_L56P_3_U8 PM_IO_51 U7 18 IO_L56N_3_U7 PM_IO_52 Y1 18 IO_L57P_3_Y1 PM_IO_53 W1 18 IO_L57N_3/VREF_3_W1 PM_IO_54 V4 18 IO_L58P_3_V4 PM_IO_55 V3 18 IO_L58N_3_V3 PM_IO_56 U9 18 IO_L59P_3_U9 PM_IO_57 T9 18 IO_L59N_3_T9 PM_IO_58 W2 18 IO_L60P_3_W2 PM_IO_59 V2 18 IO_L60N_3_V2 PM_IO_60 U5 18 IO_L85P_3_U5 PM_IO_61 U4 18 IO_L85N_3_U4 PM_IO_62 T8 18 IO_L86P_3_T8 PM_IO_63 T7 18 IO_L86N_3_T7 PM_IO_64 U3 18 IO_L87P_3_U3 PM_IO_65 U2 SCH P/N 0381171-02 18 IO_L87N_3/VREF_3_U2 PM_IO_66 T4 ART P/N 0531311-02 18 IO_L88P_3_T4 PM_IO_67 T3 FAB P/N 1280333-02 18 IO_L88N_3_T3 PM_IO_68 T6 18 IO_L89P_3_T6 PM_IO_69 T5 18 IO_L89N_3_T5 PM_IO_70 V1 Title: ML310 VIRTEX-II PRO PLAFTORM 18 IO_L90P_3_V1 A PM_IO_71 U1 18 IO_L90N_3_U1 BANK3: PM LVDS IO A Date: 10-6-2003_14:59 Ver: X.X Sheet Size: B Rev: X Sheet 8 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 VCC2V5 XC2VP20-BANK4 R429 FF896 VRN_BANK4 9 (DIE DOWN) 49.9 U37 VRN_BANK4 AH8 9 IO_L06P_4/VRN_4_AH8 R432 9 VRP_BANK4 AG8 IO_L06N_4/VRP_4_AG8 VCC2V5 VRP_BANK4 D 9 D 49.9 9,19,20,46 FPGA_INIT AF7 IO_L01P_4/INIT_B_AF7 VCCO_4_AB10 AB10 AG6 AB11 NC IO_L01N_4/DOUT_AG6 VCCO_4_AB11 TRC_CLK_R AD9 AB12 9 IO_L02P_4/D1_AD9 VCCO_4_AB12 ATD_17 AC9 AB13 19 IO_L02N_4/D0_AC9 VCCO_4_AB13 TRC_TS1O AH7 AA10 19 IO_L03P_4/D3_AH7 VCCO_4_AA10 ATD_16 AG7 AA11 19 IO_L03N_4/D2_AG7 VCCO_4_AA11 TRC_TS2E AD8 AA12 19 IO_L05_4/No_Pair_AD8 VCCO_4_AA12 TRC_TS3 AD10 AA13 19 IO_L07P_4/VREF_4_AD10 VCCO_4_AA13 ATD_18 AC10 AA14 19 IO_L07N_4_AC10 VCCO_4_AA14 TRC_TS5 AE8 AA15 19 IO_L08P_4_AE8 VCCO_4_AA15 TRC_TS6 AE7 19 IO_L08N_4_AE7 NOTE: TRC_CLK RESISTOR ALLOWS CLOCK TERMINATION ATD_8 AK8 19 IO_L09P_4/VREF_4_AK8 ATD_9 AJ8 19 IO_L09N_4_AJ8 TO BE ADJUSTED INDEPENDENTLY OF OTHER I/O. ATD_15 AD11 19 IO_L37P_4_AD11 ATD_19 AC11 19 IO_L37N_4_AC11 ATD_13 AF9 19 IO_L38P_4_AF9 TRC_CLK R31 TRC_CLK_R 19 AATTDD__1120 AAG1F80 IO_L38N_4_AF8 19 9 19 IO_L39P_4_AG10 TRC_TS1E AF10 19 IO_L39N_4_AF10 24.9 19 TRC_TS2O AD12 IO_L43P_4_AD12 ATD_14 AC12 19 IO_L43N_4_AC12 ATD_11 AE10 19 IO_L44P_4_AE10 TRC_TS4 AE9 19 IO_L44N_4_AE9 CPU_TDI AJ9 19 IO_L45P_4/VREF_4_AJ9 CPU_TDO_TMP AH9 19 IO_L45N_4_AH9 CPU_TMS AD13 19 IO_L46P_4_AD13 C VCC2V5 19 CPU_TCK AC13 IO_L46N_4_AC13 C CPU_TRST_N AE12 19 IO_L47P_4_AE12 CPU_HALT_N AE11 R440 19 IO_L47N_4_AE11 FPGA_INIT AH11 9,19,20,46 NC IO_L48P_4_AH11 FPGA_LED_USER1 AH10 4.75K 47 IO_L48N_4_AH10 FPGA_LED_USER2 AC14 47 IO_L49P_4_AC14 OPB_BUS_ERROR AB14 46 IO_L49N_4_AB14 PLB_BUS_ERROR AF11 46 IO_L50_4/No_Pair_AF11 AG11 NC IO_L53_4/No_Pair_AG11 SPI_DATA_IN AK10 45 IO_L54P_4_AK10 SPI_DATA_OUT AJ10 45 IO_L54N_4_AJ10 SPI_DATA_CS_N AF13 45 SPI_CLK AF12 IO_L56P_4_AF13 45 IO_L56N_4_AF12 AH13 NC IO_L57P_4/VREF_4_AH13 AG13 NC IO_L57N_4_AG13 PM_IO_72 AC15 15,18 IO_L67P_4_AC15 PM_IO_73 AB15 15,18 IO_L67N_4_AB15 PM_IO_74 AE14 15,18 IO_L68P_4_AE14 PM_IO_75 AD14 15,18 IO_L68N_4_AD14 PM_IO_76 AG14 15,18 IO_L69P_4/VREF_4_AG14 PM_IO_77 AF14 15,18 IO_L69N_4_AF14 AE15 NC IO_L73P_4_AE15 AD15 NC IO_L73N_4_AD15 LVDS_CLKEXT_P AJ15 6,9,18 IO_L75P_4/GCLK0P_AJ15 VCC2V5 6,9,18 LVDS_CLKEXT_N AH15 IO_L75N_4/GCLK1S_AH15 PM_CLK_BOT AG15 B 18 IO_L74P_4/GCLK2P_AG15 B SYSACE_FPGA_CLK AF15 9 IO_L74N_4/GCLK3S_AF15 R421 4.75K LVDS_CLKEXT_P R422 6,9,18 SYSACE_CLK_OE 5 0 R414 LVDS_CLKEXT_N 6,9,18 100 VCC2V5 VCC2V5 X8 1 4 OE VCC R411 C542 SYSACE_FPGA_CLK OSC 9 0.1UF SCH P/N 0381171-02 34.0 ART P/N 0531311-02 R412 2 3 SYSACE_CLK_OSC SYSACE_CLK_R FAB P/N 1280333-02 GND OUT 18.2 SG-636PDE R410 33.0000MHZ SYSACE_CLK Title: ML310 VIRTEX-II PRO PLAFTORM 20 A 34.0 BANK4: TRACE, CPU DEBUG, PM I/O A Date: 1-5-2004_13:05 Ver: X.X Sheet Size: B Rev: X Sheet 9 of 52 Drawn By XXX 4 3 2 1 4 3 2 1 XC2VP20-BANK5 VCC2V5 FF896 R386 10,11,12,21,23 VREF_DDR (DIE DOWN) VRN_BANK5 U37 10 49.9 10 VRN_BANK5 AG23 IO_L06P_5/VRN_5_AG23 10 VRP_BANK5 AH23 IO_L06N_5/VRP_5_AH23 VCC2V5 D D R375 10 DDR_CLK_FB AG25 IO_L01P_5/CS_B_AG25 VCCO_5_AB18 AB18 VRP_BANK5 AF24 AB19 10 NC IO_L01N_5/RDWR_B_AF24 VCCO_5_AB19 AC22 AB20 NC IO_L02P_5/D7_AC22 VCCO_5_AB20 49.9 NC AD22 IO_L02N_5/D6_AD22 VCCO_5_AB21 AB21 DDR_CKE0 AG24 AA16 21,22 IO_L03P_5/D5_AG24 VCCO_5_AA16 DDR_CKE1 AH24 AA17 21,22 IO_L03N_5/D4_AH24 VCCO_5_AA17 AD23 AA18 NC IO_L05_5/No_Pair_AD23 VCCO_5_AA18 AC21 AA19 NC IO_L07P_5_AC21 VCCO_5_AA19 AD21 AA20 IO_L07N_5/VREF_5_AD21 VCCO_5_AA20 AE24 AA21 NC IO_L08P_5_AE24 VCCO_5_AA21 DDR_A12 AE23 21,22 IO_L08N_5_AE23 DDR_A11 AJ23 21,22 IO_L09P_5_AJ23 AK23 IO_L09N_5/VREF_5_AK23 AC20 NC IO_L37P_5_AC20 AD20 NC IO_L37N_5_AD20 DDR_A09 AF23 21,22 IO_L38P_5_AF23 DDR_A07 AF22 21,22 IO_L38N_5_AF22 DDR_A06 AF21 21,22 DDR_A04 AG21 IO_L39P_5_AF21 21,22 IO_L39N_5_AG21 AC19 NC IO_L43P_5_AC19 AD19 NC IO_L43N_5_AD19 AE22 NC IO_L44P_5_AE22 VREF_DDR AE21 10,11,12,21,23 NC IO_L44N_5_AE21 DDR_A08 AH22 21,22 IO_L45P_5_AH22 AJ22 IO_L45N_5/VREF_5_AJ22 C157 C156 AC18 NC IO_L46P_5_AC18 C 0.1UF 0.01UF AD18 C NC IO_L46N_5_AD18 AE20 NC IO_L47P_5_AE20 AE19 DDR_A05 NC AH21 IO_L47N_5_AE19 21,22 DDR_A01 AH20 IO_L48P_5_AH21 21,22 IO_L48N_5_AH20 AB17 NC IO_L49P_5_AB17 AC17 NC IO_L49N_5_AC17 DDR_A00 AF20 21,22 DDR_A10 AG20 IO_L50_5/No_Pair_AF20 21,22 IO_L53_5/No_Pair_AG20 DDR_A03 AJ21 21,22 IO_L54P_5_AJ21 DDR_A02 AK21 21,22 DDR_BA0 AF19 IO_L54N_5_AK21 21,22 DDR_S1_N AF18 IO_L56P_5_AF19 21,22 DDR_BA1 AG18 IO_L56N_5_AF18 21,22 IO_L57P_5_AG18 AH18 IO_L57N_5/VREF_5_AH18 AB16 NC IO_L67P_5_AB16 AC16 NC IO_L67N_5_AC16 AD17 DDR_S0_N NC AE17 IO_L68P_5_AD17 21,22 DDR_CAS_N AF17 IO_L68N_5_AE17 21,22 IO_L69P_5_AF17 AG17 DDR_WE_N AD16 IO_L69N_5/VREF_5_AG17 21,22 DDR_RAS_N AE16 IO_L73P_5_AD16 21,22 IO_L73N_5_AE16 DDR_CLK_FB AF16 10 IO_L74P_5/GCLK4P_AF16 USER_CLKSYS AG16 10 IO_L74N_5/GCLK5S_AG16 LVDS_CLKLOC_P AH16 B 5,10 IO_L75P_5/GCLK6P_AH16 B VCC2V5 5,10 LVDS_CLKLOC_N AJ16 IO_L75N_5/GCLK7S_AJ16 R367 X6 1 14 OE1 VCC1 LVDS_CLKLOC_P 4.75K 5,10 OSC R408 C446 4 11 LVDS_CLKLOC_N OE2 VCC2 5,10 0.1UF 100 R366 7 8 USER_CLKSYS_R USER_CLKSYS GND OUT 10 24.9 MB2100H 100.0000MHZ NOSTUFF XS6 SOCKETED 14-PIN DIP SCH P/N 0381171-02 ART P/N 0531311-02 FAB P/N 1280333-02 Title: ML310 VIRTEX-II PRO PLAFTORM A BANK5: DDR A Date: 12-2-2003_13:35 Ver: X.X Sheet Size: B Rev: X Sheet 10 of 52 Drawn By XXX 4 3 2 1

Description:
PCB FABRICATION. SCHEMATICS. XILINX PART NUMBERS. 0381171-02. 0531311-02. 1280333-02. NOSTUFF ITEMS ARE NOT POPULATED ON
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