Partial Reconfiguration on FPGAs: Architectures, Tools and Applications

306 Pages·2013·12.437 MB·English

by  Dirk Koch (auth.)

Partial Reconfiguration on FPGAs
Lecture Notes in Electrical Engineering
Volume 153
Forfurthervolumes:
http://www.springer.com/series/7818
Dirk Koch
Partial Reconfiguration
on FPGAs
Architectures, Tools and Applications
123
DirkKoch
UniversityofOslo
Oslo,Norway
ISBN978-1-4614-1224-3 ISBN978-1-4614-1225-0(eBook)
DOI10.1007/978-1-4614-1225-0
SpringerNewYorkHeidelbergDordrechtLondon
LibraryofCongressControlNumber:2012932628
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Preface
Theresearchonpartialruntimereconfigurationhasa historythatis aslongasthe
greathistoryofFPGAs.However,despiteatimeframeofmorethantwodecades,
theworkonpartialreconfigurationhasnotfounditswayintocommercialsystems
yet, and is still considered very exotic. This is an interesting phenomenon as the
benefitsinsavingcostlyFPGAresourcesandpowerconsumptioncanbesubstantial.
One reason for this phenomenon is that implementing partially reconfigurable
systems is by far more difficultwith ASIC-like design tools when comparedwith
simplybuildingstaticonlysystemsthatomitthisnicefeature.
There is a long list of system constraints, FPGA specific issues, problems
with the design tools, documentationsecrets, and missing techniquesfor resource
managementat runtime, that have to be processed to get a reconfigurable system
running. Moreover, all these obstacles have to be understood in order to be
able to build reconfigurable systems which gain a significant improvement over
conventional static implementations, and which are reliable. In other words, it is
typicallynotsufficienttohaveasimplifiedproofofconceptimplementationinorder
tobuildreconfigurablesystemsonalargescale.
Throughout this book, all major obstacles will be explained together with
solutions. The goal of this book is to tackle the problems that come along with
partialruntimereconfiguration,inasystematicway.Thisisdonebyproposingtools
thatare aware of the issues related to partialruntimereconfiguration,hidingmost
low level implementation details from a design engineer. By doing this, an error
pronedesignflowisomittedandreproducibleresultscanbeguaranteed.
ThisbookdoesnotprovideageneralintroductionintoFPGAdesigntechniques,
which is already nicely covered in numerous textbooks. Here, the focus is put,
in particular, on the effects of partial runtime reconfiguration that are not deeply
coveredbyothertextbooksasyet.However,readersofthisbookarenotexpectedto
havedeepknowledgeabouthardwaredesignandFPGA technology;allnecessary
technicalbasicshavebeenprovided.
This book has been written for design engineers who are interested in investi-
gatingruntimereconfiguration.Moreover,the bookalso targetsgraduatestudents,
lecturers and researchers working in the field. The book provides theoretical and
v
vi Preface
practical background, as well as design experience gathered through a decade of
workingwithreconfigurabledevicesandsystems.
Finally, this is the first issue of this book, and despite the review effort, there
are probably some remaining mistakes. Therefore, I will be grateful to receive
yourcommentsinthisregard.Moreover,thisbookreflectsmanyyearsofpersonal
experience,andtheknowledgesharedbymanygreatcolleaguesandstudentswhom
ImetsincestartingmyworkonFPGAs.However,manyreadershavegatheredtheir
ownexperiencewhenusingpartialreconfiguration,andIamverypleasedwhenever
theysharetheirexperienceswithme.
Oslo,Norway DirkKoch
Contents
1 Introduction .................................................................. 1
1.1 BasicDefinitionsonReconfigurableComputing..................... 3
1.2 ReconfigurableFPGATechnology.................................... 6
1.2.1 ReconfigurableLogiconFPGAs ............................. 6
1.2.2 ReconfigurableRoutingonFPGAs........................... 9
1.2.3 PuttingThingsTogether:ASimpleFPGAArchitecture .... 11
1.3 BenefitsofPartialReconfiguration.................................... 15
1.3.1 AreaandPowerReduction.................................... 17
1.3.2 PerformanceImprovement.................................... 18
1.3.3 FastSystemStart .............................................. 21
1.4 BasicModelofPartialReconfiguration............................... 22
1.5 PartialReconfigurationinTime ....................................... 24
1.5.1 Sub-CycleReconfiguration ................................... 24
1.5.2 Single-CycleReconfiguration................................. 27
1.5.3 Multi-CycleReconfiguration.................................. 29
1.6 PartialReconfigurationinSpaceandTime ........................... 29
1.6.1 SmallNetlistManipulations .................................. 30
1.6.2 IslandStyleReconfiguration.................................. 31
1.6.3 FPGAFootprintandModuleFootprint....................... 33
1.6.4 One-dimensionalSlot-styleReconfiguration................. 36
1.6.5 Two-dimensionalGrid-styleReconfiguration................ 37
1.7 PartialReconfigurationasFPGAContextSwitching................. 38
1.8 Overview................................................................ 40
2 Intra-FPGA Communication Architectures
forReconfigurableSystems................................................. 43
2.1 PreconsiderationsonFlexibilityandModulePlacement............. 44
2.2 EfficiencyPreconsiderations........................................... 45
2.3 FPGAArchitectureModel............................................. 48
2.4 RelatedWorkonCommunicationforReconfigurableSystems...... 53
2.4.1 CircuitSwitching.............................................. 54
vii
viii Contents
2.4.2 NetworksonaChip ........................................... 58
2.4.3 Buses........................................................... 60
2.4.4 PhysicalImplementationTechniques......................... 65
2.4.5 ProxyLogic.................................................... 71
2.4.6 ZeroLogicOverheadIntegration............................. 72
2.5 Bus-BasedCommunicationforReconfigurableSystems............. 75
2.5.1 SharedWriteSignals.......................................... 77
2.5.2 DedicatedWriteSignals....................................... 80
2.5.3 SharedReadSignals........................................... 88
2.5.4 DedicatedReadSignals....................................... 94
2.5.5 Module-to-ModuleReCoBusCommunication .............. 100
2.5.6 BusesforTwo-dimensionalPlacement....................... 102
2.6 Point-to-PointCommunication ........................................ 104
2.6.1 One-dimensionalOnlineCircuitSwitching.................. 107
2.6.2 Two-dimensionalOnlineCircuitSwitching.................. 110
2.7 ExperimentalResults................................................... 114
2.7.1 ReCoBusTimingCharacteristics............................. 115
2.7.2 LogicCostoftheReCoBusArchitecture .................... 124
2.7.3 TheImpactofModularizationonthePhysical
Implementation................................................ 129
2.7.4 Glitch-freeReconfiguration................................... 131
2.7.5 CommunicationforTwo-dimensionalModulePlacement .. 137
2.8 ChapterContributionsandDiscussion ................................ 146
3 BuildingPartiallyReconfigurableSystems:MethodsandTools ....... 149
3.1 AFrameworkforComponent-BasedReconfigurable
SystemDesign.......................................................... 150
3.2 ReCoBus-Builder:ABuilderforReconfigurableSystems........... 153
3.2.1 Floorplanning.................................................. 155
3.2.2 ReCoBusGeneration.......................................... 156
3.2.3 ConnectionBarGeneration................................... 158
3.2.4 RoutingConstraints(Blocking)............................... 159
3.2.5 TimingSpecification .......................................... 162
3.2.6 BitstreamAssemblyandHardwareLinking ................. 162
3.2.7 SimulatingRuntimeReconfiguration......................... 164
3.3 Core-BasedSystemDesign............................................ 167
3.4 RuntimeReconfiguration .............................................. 168
3.4.1 HorizontalBitstreamRelocation.............................. 169
3.4.2 VerticalBitstreamRelocation................................. 170
3.4.3 SmallBitstreamManipulations............................... 173
3.5 HighSpeedReconfiguration........................................... 174
3.5.1 ConfigurationPrefetching..................................... 174
3.5.2 ConfigurationPortOverclocking............................. 175
3.5.3 HardwareAcceleratedBitstreamDecompression ........... 176
3.5.4 AlgorithmsforBitstreamCompression ...................... 179
Contents ix
3.5.5 BenchmarkingBitstreamDecompressionAccelerators..... 189
3.5.6 High-speedDefragmentation ................................. 192
3.6 ChapterSummaryandContributions.................................. 198
4 Self-adaptiveReconfigurableNetworks................................... 199
4.1 HardwareCheckpointing............................................... 201
4.1.1 RelatedWorkonHardwareCheckpointing .................. 202
4.1.2 FSM-basedTaskModel....................................... 203
4.1.3 CheckpointingInputandOutputStates ...................... 205
4.2 AccessingModuleStates............................................... 207
4.2.1 Memory-MappedStateAccess ............................... 208
4.2.2 StateAccessviaScanChains................................. 209
4.2.3 StateAccessviaShadowScanChains ....................... 211
4.2.4 AutomaticHardwareTransformationwithStateAccess..... 211
4.2.5 FurtherModuleTransformationsandLimitations........... 213
4.2.6 ExperimentalEvaluation...................................... 213
4.2.7 CheckpointingviaFPGAReadbackTechniques............. 216
4.2.8 HardwareCheckpointingin Heterogeneous
FPGAEnvironments .......................................... 219
4.3 Hardware/SoftwareMorphing......................................... 220
4.3.1 RelatedWorkonHardware/SoftwareMorphing............. 220
4.3.2 ModelingHardware/SoftwareMorphing..................... 222
4.3.3 StateTranslation............................................... 224
4.3.4 DesignFlowforImplementingMorphableTasks ........... 227
4.3.5 MorphingCaseStudy ......................................... 229
4.4 ChapterSummary ...................................................... 230
5 ReconfigurableCPUInstructionSetExtensions ......................... 235
5.1 On-FPGACommunicationforCustomInstructions.................. 236
5.2 ZeroLogicOverheadIntegration...................................... 238
5.2.1 StaticSystemConstraints..................................... 239
5.2.2 PartialModuleConstraints.................................... 239
5.2.3 CommunicationBindingbyWireAllocation................ 240
5.3 Implementing Reconfigurable Instructions
withtheReCoBus-Builder............................................. 241
5.4 CaseStudyonCustomInstructions ................................... 242
5.4.1 StaticSystemImplementation................................ 243
5.4.2 ReconfigurableInstructions................................... 245
5.4.3 ResultsandOverheadAnalysis............................... 245
6 ConcludingRemarks........................................................ 249
6.1 FutureDirections....................................................... 251
A Appendix ..................................................................... 253
A.1 TheToolGOAHEAD ................................................... 253
A.2 AReconfigurableHello WorldSystem........................... 255