Table Of ContentParallel-sampling ADC architecture for power-efficient
broadband multi-carrier systems
Citation for published version (APA):
Lin, Y. (2014). Parallel-sampling ADC architecture for power-efficient broadband multi-carrier systems. [Phd
Thesis 1 (Research TU/e / Graduation TU/e), Electrical Engineering]. Technische Universiteit Eindhoven.
https://doi.org/10.6100/IR782336
DOI:
10.6100/IR782336
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Published: 09/12/2014
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Download date: 17. Feb. 2023
Parallel-sampling ADC Architecture for
Power-efficient Broadband Multi-carrier Systems
Yu Lin
This research work was supported by the Technology Foundation (STW) of the Netherlands
under project 06655, and was done in cooperation with NXP Semiconductors, Central R&D,
Mixed-Signal Circuits and Systems Group.
Cover designed by Dr. Yanliu Lin
Copyright ©2014 by Yu Lin
Parallel-sampling ADC architecture for power-efficient broadband multi-carrier systems
A catalogue record is available from the Eindhoven University of Technology Library
ISBN: 978-90-386-3736-5
Parallel-sampling ADC architecture for
power-efficient broadband multi-carrier systems
PROEFSCHRIFT
ter verkrijging van de graad van doctor aan de Technische
Universiteit Eindhoven, op gezag van de rector magnificus
prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen
door het College voor Promoties, in het openbaar te
verdedigen op dinsdag 9 december 2014 om 16:00 uur
Door
Yu Lin
geboren te Raoping, China
Dit proefschrift is goedgekeurd door de promotoren en de samenstelling
van de promotiecommissie is als volgt:
voorzitter: prof.dr.ir. A.C.P.M. Backx
promotor: prof.dr.ir. A.H.M. van Roermund
copromotor: dr.ir. J.A.Hegt
leden: prof.dr.ir. A.J.M. van Tuijl (UT)
prof.dr.ir. M. Steyaert (KU Leuven)
prof.dr.ir. P.G.M. Baltus
adviseurs: dr. K. Doris MSc (NXP Semiconductors)
dr. P.J. Quinn MSc (Xilinx)
林艳柳 林岱睿，林沅睿
To my parents, wife ( ) and daughters ( )
TABLE OF CONTENTS
List of symbols and abbreviations .............................................................................. 1
Chapter 1: Introduction .............................................................................................. 5
1.1. Background .................................................................................................... 5
1.2. Thesis aim and outline ................................................................................... 6
Chapter 2: Enhancing ADC performance by exploiting signal properties ............ 9
2.1. Introduction to analog-to-digital converters .................................................. 9
2.2. ADC performance parameters ..................................................................... 11
2.2.1. Conversion accuracy ............................................................................ 11
2.2.2. Bandwidth ............................................................................................ 15
2.2.3. Power .................................................................................................... 15
2.2.4. ADC Figure-of-Merit ........................................................................... 15
2.3. ADC performance limitations and trends .................................................... 16
2.4. ADC architectures ....................................................................................... 20
2.5. Exploiting signal properties ......................................................................... 23
2.6. Conclusion ................................................................................................... 27
Chapter 3: Parallel-sampling ADC architecture for multi-carrier signals .......... 30
3.1. Introduction to multi-carrier transmission ................................................... 30
3.2. Statistical amplitude properties of multi-carrier signals .............................. 32
3.3. ADC requirements for multi-carrier signals ................................................ 36
3.4. Power reduction techniques for thermal-noise limited ADCs ..................... 42
i
3.5. A parallel-sampling ADC architecture ....................................................... 46
3.5.1. Principle of the parallel-sampling ADC architecture .......................... 47
3.5.2. Advantages of the parallel-sampling architecture ............................... 49
3.5.3. Impact of mismatch between signal paths ........................................... 54
3.6. Implementation options............................................................................... 56
3.7. Conclusions ................................................................................................. 60
Chapter 4: Implementations of the parallel-sampling ADC architecture ........... 64
4.1. Parallel-sampling architecture applied to a pipeline ADC .......................... 64
4.1.1. Pipeline ADCs architecture ................................................................. 65
4.1.2. A parallel-sampling first stage for a pipeline ADC ............................. 66
4.1.3. Implementation and operation of the first stage .................................. 69
4.1.4. Simulation and comparison ................................................................. 74
4.2. Parallel-sampling architecture applied to a TI SAR ADC .......................... 79
4.2.1. A hierarchical TI-SAR ADC architecture ........................................... 79
4.2.2. A parallel-sampling frontend stage for a TI-SAR ADC ...................... 80
4.2.3. Implementation and operation ............................................................. 83
4.2.4. Simulation results ................................................................................ 86
4.3. Design of a 1GS/s 11-bit parallel-sampling ADC ...................................... 89
4.3.1. Architecture and operation overview ................................................... 90
4.3.2. Circuit Implementation ........................................................................ 91
4.3.3. Layout and testchip implementation .................................................. 101
4.3.4. Measurement setup ............................................................................ 103
ii
4.3.5. Experimental results ........................................................................... 105
4.3.6. Performance summary........................................................................ 115
4.3.7. Comparison with state-of-the-art ....................................................... 116
4.4. Conclusions ............................................................................................... 118
Chapter 5: Conclusions and recommendations .................................................... 124
5.1. Conclusions ............................................................................................... 124
5.2. Recommendations for future research ....................................................... 125
Appendix: A dynamic latched comparator for low voltage applications ........... 127
List of publications .................................................................................................. 136
Summary .................................................................................................................. 138
Acknowledgement .................................................................................................... 140
Curriculum vitae ..................................................................................................... 140
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