On-chip communication architectures : system on chip interconnect

541 Pages·2008·30.339 MB·English

by  Sudeep Pasricha, Nikil Dutt

On-Chip Communication
Architectures
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On-Chip Communication

Architectures
System on Chip Interconnect
Sudeep Pasricha – Nikil Dutt
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Library of Congress Cataloging-in-Publication Data
Pasricha, Sudeep..
On-chip communication architectures: system on chip interconnect/Sudeep Pasricha, Nikil Dutt.
p. cm.
Includes bibliographical references and index.
ISBN-13: 978-0-12-373892-9 (hardback: alk. paper) 1. Systems on a chip. 2. Microcomputers—Buses
3. Computer architecture. 4. Interconnects (Integrated circuit technology) I. Dutt, Nikil. II. Title.
TK7895.E42P4 2008
621.3815—dc22
2008004691
ISBN: 978-0-12-373892-9
For information on all Morgan Kaufmann publications, visit our
Web site at www.mkp.com orwww.books.elsevier.com
08 09 10 11 12 13 10 9 8 7 6 5 4 3 2 1
Printed in the United States of America
Contents
Preface ix
About the Authors xiii
Acknowledgments xv
List of Contributors xvii
CHAPTER 1 Introduction ........................................................................................ 1
1.1 Trends in System-On-Chip Design .....................................................1
1.2 Coping with Soc Design Complexity ................................................3
1.3 ESL Design Flow ................................................................................4
1.4 On-Chip Communication Architectures: A Quick Look .....................6
1.5 Book Outline ...................................................................................12
CHAPTER 2 Basic Concepts of Bus-Based Communication
Architectures .................................................................................... 17
2.1 Terminology ....................................................................................18
2.2 Characteristics of Bus-Based Communication Architectures ...........19
2.3 Data Transfer Modes ........................................................................28
2.4 Bus Topology Types .........................................................................33
2.5 Physical Implementation of Bus Wires ............................................37
2.6 Discussion: Buses in the DSM Era ....................................................38
2.7 Summary ..........................................................................................39
CHAPTER 3 On-Chip Communication Architecture Standards ............................... 43
3.1 Standard On-Chip Bus-Based Communication Architectures ..........44
3.2 Socket-Based On-Chip Bus Interface Standards ...............................88
3.3 Discussion: Off-Chip Bus Architecture Standards ............................96
3.4 Summary ..........................................................................................97
CHAPTER 4 Models for Performance Exploration .............................................. 1 01
4.1 Static Performance Estimation Models ..........................................102
4.2 Dynamic (Simulation-Based) Performance Estimation Models ......111
4.3 Hybrid Communication Architecture Performance Estimation
Approaches ....................................................................................132
4.4 Summary ........................................................................................138
CHAPTER 5 Models for Power and Thermal Estimation ......................................1 43
5.1 Bus Wire Power Models .................................................................145
5.2 Comprehensive Bus Architecture Power Models ..........................153
5.3 Bus Wire Thermal Models ..............................................................167
vi Contents
5.4 Discussion: PVT Variation-Aware Power Estimation ....................174
5.5 Summary .....................................................................................179
CHAPTER 6 Synthesis of On-Chip Communication
Architectures .............................................................................. 185
6.1 Bus Topology Synthesis ...............................................................187
6.2 Bus Protocol Parameter Synthesis ...............................................196
6.3 Bus Topology and Protocol Parameter Synthesis .........................205
6.4 Physical Implementation Aware Synthesis ..................................216
6.5 Memory–Communication Architecture Co-synthesis ..................230
6.6 Discussion: Physical and Circuit Level Design of On-Chip
Communication Architectures ....................................................240
6.7 Summary .....................................................................................243
CHAPTER 7 Encoding Techniques for On-Chip Communication
Architectures ...............................................................................253
7.1 Techniques for Power Reduction ................................................255
7.2 Techniques for Reducing Capacitive Crosstalk Delay .................278
7.3 Techniques for Reducing Power and Capacitive
Crosstalk Effects ..........................................................................282
7.4 Techniques for Reducing Inductive Crosstalk Effects .................284
7.5 Techniques for Fault Tolerance and Reliability ............................287
7.6 Summary .....................................................................................292
CHAPTER 8 Custom Bus-Based On-Chip Communication
Architecture Design ....................................................................3 01
8.1 Split Bus Architectures ................................................................301
8.2 Serial Bus Architectures ..............................................................309
8.3 CDMA-Based Bus Architectures ...................................................310
8.4 Asynchronous Bus Architectures ................................................313
8.5 Dynamically Reconfi gurable Bus Architectures ..........................318
8.6 Summary .....................................................................................336
CHAPTER 9 On-Chip Communication Architecture Refi nement
and Interface Synthesis. .............................................................. 341
9.1 On-Chip Communication Architecture Refi nement ....................343
9.2 Interface Synthesis ......................................................................346
9.3 Discussion: Interface Synthesis ...................................................361
9.4 Summary .....................................................................................361
CHAPTER 10 Verifi cation and Security Issues in On-Chip
Communication Architecture Design ........................................... 3 67
10.1 Verifi cation of On-Chip Communication Protocols ....................369
10.2 Compliance Verifi cation for IP Block Integration .......................376
10.3 Basic Concepts of SoC Security ..................................................388
Contents vii
10.4 Security Support in Standard Bus Protocols ...............................391
10.5 Communication Architecture Enhancements for
Improving SoC Security ..............................................................391
10.6 Summary .....................................................................................395
CHAPTER 11 Physical Design Trends for Interconnects .................................... 403
11.1 DSM Interconnect Design ..........................................................405
11.2 Low Power, High Speed Circuit Design Techniques ...................408
11.3 Global Power Distribution Networks .........................................417
11.4 Clock Distribution Networks .....................................................421
11.5 3-D Interconnects .......................................................................427
11.6 Summary and Concluding Remarks ...........................................429
CHAPTER 12 Networks-On-Chip ....................................................................... 439
12.1 Network Topology ......................................................................443
12.2 Switching Strategies ...................................................................448
12.3 Routing Algorithms .....................................................................451
12.4 Flow Control ..............................................................................454
12.5 Clocking Schemes ......................................................................458
12.6 Quality of Service .......................................................................459
12.7 NoC Architectures ......................................................................459
12.8 NoC Status and Open Problems .................................................464
12.9 Summary .....................................................................................466
CHAPTER 13 Emerging On-Chip Interconnect Technologies .............................. 473
13.1 Optical Interconnects .................................................................474
13.2 RF/Wireless Interconnects .........................................................483
13.3 CNT Interconnects .....................................................................490
13.4 Summary .....................................................................................501
Index... ................................................................................................ .509
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Preface
Digital electronic devices such as mobile phones, video game consoles, and net-
work routers typically contain one or more electronic (integrated circuit) chips
that are composed of several components such as processors, dedicated hard-
ware engines and memory, and are referred to as system-on-chip (SoC). These SoC
designs are rapidly becoming more complex, in order to handle the ever increas-
ing complexity of applications, fueled by the onset of the digital convergence era.
Continuing improvements in process technology have allowed the integration of
components previously connected at the board level onto a single chip, which
further adds to the complexity.
The components on a SoC are connected together by an on-chip communica-
tion architecture backbone that supports all inter-component data communica-
tion, both within the chip as well as with external devices (e.g., external fl ash
drives). These SoC communication architectures have been shown to have a sig-
nifi cant impact on the performance, power consumption, cost, and design time
of SoCs. Indeed, modern SoC design processes are increasingly becoming c om-
munication-centric, since reusable components (e.g., processors, memories, etc.),
as well as custom hardware blocks and interfaces, need to be connected via a
communication architecture fabric, with the goal of meeting various design con-
straints such as cost, performance, power/energy, and reliability. The move toward
higher levels of abstraction have led to the notion of e lectronic system level (ESL)
design, where system architects and application designers are able to capture sys-
tem functionality and map desired system functionality onto a range of software
and hardware confi gurations that exhibit differing performance, cost, power/
energy, reliability, and other design metrics. A key step within an ESL design fl ow
is the effi cient use of an on-chip communication architecture fabric. Consequently,
there has been a large body of work on modeling abstractions, communication
protocols and standards, as well as active research on communication architecture
design and exploration.
This book aims to serve as a comprehensive reference on the concepts,
research, and trends in on-chip communication architecture design. We describe
the basic concepts and attributes of on-chip communication architectures, to
familiarize the reader with intricate details of on-chip communication architecture
design and the problems facing designers. This is followed by an expansive sur-
vey of research efforts in this area, spanning the past several years, and addressing
some of the major issues in on-chip communication architecture design. Finally,
we present some of the trends that will shape future research in the area of on-
chip communication architecture design. ix