On and Off-Chip Crosstalk Avoidance in VLSI Design

249 Pages·2010·5.547 MB·English

by  Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri (auth.)

On and Off-Chip Crosstalk Avoidance
in VLSI Design
· ·
Chunjie Duan Brock J. LaMeres Sunil P. Khatri
On and Off-Chip
Crosstalk Avoidance
in VLSI Design
2123
Authors
Dr.ChunjieDuan Dr.BrockJ.LaMeres
MitsubishiElectricResearch MontanaStateUniversity
Laboratories(MERL) Dept.Electrical&ComputerEngineering
201Broadway 533CobleighHall
Cambridge,MA02139 Bozeman,MT59717
USA USA
[email protected] [email protected]
Dr.SunilP.Khatri
TexasA&MUniversity
Dept.Electrical&ComputerEngineering
214ZachryEngineeringCenter
CollegeStation,TX77843-3128
USA
[email protected]
ISBN978-1-4419-0946-6 e-ISBN978-1-4419-0947-3
DOI10.1007/978-1-4419-0947-3
SpringerNewYorkDordrechtHeidelbergLondon
LibraryofCongressControlNumber:2009944062
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Preface
One of the greatest challenges in Deep Sub-Micron (DSM) design is inter-wire
crosstalk,whichbecomessignificantwithshrinkingfeaturesizesofVLSIfabrication
processes and greatly limits the speed and increases the power consumption of an
IC.Thismonographpresentsapproachestoavoidcrosstalkinbothon-chipaswell
asoff-chipbusses.
Theresearchworkpresentedinthefirstpartofthismonographfocusesoncrosstalk
avoidance with bus encoding, one of the techniques that effectively mitigates the
impactofon-chipcapacitivecrosstalkandimprovesthespeedandpowerconsump-
tionofthebusinterconnect.Thistechniqueencodesdatabeforetransmissionover
the bus to avoid certain undesirable crosstalk conditions and thereby improves the
busspeedand/orenergyconsumption.Wefirstderivetherelationshipbetweenthe
inter-wirecapacitivecrosstalkandsignalspeedaswellaspower,andshowthedata
patterndependenceofcrosstalk.Asystemtoclassifybussesbasedondatapatterns
is introduced and serves as the foundation for all the on-chip crosstalk avoidance
encoding techniques. The first set of crosstalk avoidance codes (CACs) discussed
arememorylesscodes.Thesecodesaregeneratedusingafixedcode-bookandsolely
dependentonthecurrentinputdata,andthereforerequirelesscomplicatedCODECs.
WestudyasuiteofmemorylessCACs:from3C-freeto1C-freecodes,includingcode
design details and performance analysis. We show that these codes are more effi-
cientthanconventionalcrosstalkavoidancetechniques.WediscussseveralCODEC
design techniques that enable the construction of modular, fast and low overhead
CODECs.ThesecondsetofcodespresentedarememorybasedCACs.Comparedto
memorylesscodes,thesecodesaremoreareaefficient.ThecorrespondingCODEC
designsaremorecomplicated,however,sincetheencoding/decodingprocessesre-
quire the current input and the previous state. The memory-based codes discussed
include a 4C-free code, which requires as little as 33% overhead with simple and
fastCODECdesigns.Wealsopresenttwogeneralmemory-basedcodewordgenera-
tiontechniques,namelythe“code-pruning”-basedalgorithmandtheROBDD-based
algorithm. We then further extend the crosstalk avoidance to multi-valued bus in-
terconnects. Thecrosstalkclassificationsystemisfirstgeneralizedtomulti-valued
bussesandtwoternarycrosstalkavoidanceschemesarediscussed.Detailsaboutthe
ternarydriverandreceivercircuitdesignsarealsopresentedinthemonograph.
v
vi Preface
Advances in VLSI design and fabrication technologies have led to a dramatic
increase in the on-chip performance of integrated circuits. The transistor delay in
anintegratedcircuitisnolongerthesinglebottlenecktosystemperformanceasit
has historically been in past decades. System performance is now also limited by
theelectricalparasiticsofthepackaginginterconnect.Noisesourcessuchassupply
bounce, signal coupling, and reflections all result in reduced performance. These
factorsariseduetotheparasiticinductanceandcapacitanceofthepackaginginter-
connect.Whileadvancedpackagingcanaidinreducingtheparasitics,thecostand
timeassociatedwiththedesignofanewpackageisoftennotsuitedforthemajority
ofVLSIdesigns.Thesecondpartofthismonographpresentstechniquestomodel
and alleviate off-chip inductive crosstalk. This work presents techniques to model
andimproveperformancetheperformanceofVLSIdesignswithoutmovingtoward
advancedpackaging.Asingle,unifiedmathematicalframeworkispresentedthatpre-
dictstheperformanceofagivenpackagedependingonthepackageparasiticsand
bus configuration used. The performance model is shown to be accurate to within
10%ofanalogsimulatorresultswhicharemuchmorecomputationallyexpensive.
Usinginformationaboutthepackage,amethodologyispresentedtoselectthemost
cost-effectivebuswidthforagivenpackage. Inaddition, techniquesarepresented
toencodeoff-chipdatasoastoavoidtheswitchingpatternsthatleadtoincreased
noise.Thereducednoiselevelthatresultsfromencodingtheoff-chipdatatranslates
intoincreasedbusperformanceevenafteraccountingfortheencoderoverhead.Per-
formanceimprovementsofupto225%arereportedusingtheencodingtechniques.
Finally, a compensation technique is presented that matches the impedance of the
package interconnect to the impedance of the PCB, resulting in reduced reflected
noise. The compensation technique is shown to reduce reflected noise as much as
400%forbroadbandfrequenciesupto3GHz.Thetechniquespresentedinthiswork
aredescribedingeneraltermssoasnottolimittheapproachtoanyparticulartech-
nology.Atthesametime, thetechniquesarevalidatedusingexistingtechnologies
toprovetheireffectiveness.
TheauthorswouldliketothankEricssonWirelessCommunicationsinBoulder,
Colorado,MitsubishiElectricResearchLaboratoriesinCambridge,Massachusetts
and Agilent Technologies in Colorado Springs for funding some of the research
workspresentedinthismonograph.AgilentTechnologiesalsoprovidedinstrumen-
tation,EDAtools,andhardwareusedinthedevelopmentandanalysisoftheoff-chip
crosstalk avoidance techniques in this monograph. The authors would also like to
thank Xilinx Corporation for providing the FPGA devices and design methodolo-
giesnecessaryforprototypingthetechniquesinthismonographandevaluatingtheir
feasibility.
August2009 ChunjieDuan
BrockJ.LaMeres
SunilP.Khatri
Acknowledgements
Dr.Duanisgratefultohisparents,DerongandXingling,andhisbeautifulwife,Rui
fortheirunconditionalsupportovertheyears.Withouttheirsupport,researchwould
havebeenalotmorepainfulexperiencethanitalreadyis.
Dr.LaMereswouldliketothankhisfamilyforallofthesupporttheyhavegiven
overtheyears.Endlessthanksforofferedtohiswonderfulwife,JoAnn,andtohis
twopreciousdaughters,AlexisandKylie,whohavegivenuptoomanynightsand
weekendsoffamilytimeforthepursuitofresearchinthisarea.Theirsacrificewill
alwaysberemembered.
Dr. Khatri would like to thank his family for their support and encouragement
overtheyears, withoutwhichthisbookandmanyotherresearchendeavorswould
simplynothavebeenpossible.
vii
Contents
PartI On-ChipCrosstalkandAvoidance............................ 1
1 IntroductionofOn-ChipCrosstalkAvoidance ..................... 3
1.1 ChallengesinDeepSubmicronProcesses...................... 3
1.2 OverviewofOn-ChipCrosstalkAvoidance .................... 4
1.3 BusEncodingforCrosstalkAvoidance ........................ 9
1.4 PartIOrganization......................................... 10
2 PreliminariestoOn-ChipCrosstalk .............................. 13
2.1 ModelingofOn-ChipInterconnects .......................... 13
2.2 CrosstalkBasedBusClassification ........................... 22
2.3 BusEncodingforCrosstalkAvoidance ........................ 24
2.4 NotationandTerminology .................................. 25
3 MemorylessCrosstalkAvoidanceCodes .......................... 27
3.1 3C-FreeCACs ............................................ 27
3.1.1 ForbiddenPatternFreeCAC .......................... 28
3.1.2 ForbiddenTransitionFreeCAC ....................... 32
3.1.3 CircuitImplementationandSimulationResults .......... 35
3.2 2C-FreeCACs ............................................ 37
3.2.1 CodeConstruction .................................. 38
3.2.2 CodeCardinalityandAreaOverhead ................... 40
3.2.3 2CExperiments..................................... 42
3.3 1C-FreeBusses ........................................... 42
3.3.1 BusConfigurations .................................. 43
3.3.2 ExperimentalResults ................................ 43
3.4 Summary................................................. 44
4 CODECDesignsforMemorylessCrosstalkAvoidanceCodes ....... 47
4.1 BusPartitioningBasedCODECDesignTechniques ............. 47
4.2 GroupComplement ........................................ 48
4.2.1 ProofofCorrectness................................. 50
4.3 BitOverlapping ........................................... 51
ix
x Contents
4.4 FPF-CACCODECDesign .................................. 51
4.4.1 Fibonacci-BasedBinaryNumeralSystem ............... 52
4.4.2 Near-OptimalCODEC ............................... 53
4.4.3 OptimalCODEC.................................... 57
4.4.4 ImplementationandExperimentalResults............... 59
4.5 FTF-CACCODECDesign .................................. 65
4.5.1 MappingScheme ................................... 65
4.5.2 CodingAlgorithm................................... 66
4.5.3 ImplementationandExperimentalResults............... 67
4.6 Summary................................................. 70
5 Memory-basedCrosstalkAvoidanceCodes........................ 73
5.1 A4C-FreeCAC ........................................... 73
5.1.1 A4C-freeEncodingTechnique ........................ 73
5.1.2 AnExample........................................ 74
5.2 CodewordGenerationbyPruning ............................ 75
5.3 CodewordGenerationUsingROBDD......................... 80
kc−free
5.3.1 EfficientConstructionofG ...................... 80
m
5.3.2 AnExample........................................ 82
kc−free
5.3.3 FindingtheEffectivekC FreeBusWidthfromG .... 83
m
5.3.4 ExperimentalResults ................................ 84
5.4 Summary................................................. 85
6 Multi-ValuedLogicCrosstalkAvoidanceCodes.................... 87
6.1 BusClassificationinMulti-ValuedBusses ..................... 88
6.2 LowPowerandCrosstalkAvoidingCodingonaTernaryBus ..... 90
6.2.1 DirectBinary-TernaryMapping ....................... 90
6.2.2 4XTernaryCode.................................... 91
6.2.3 3XTernaryCode.................................... 93
6.3 CircuitImplementations .................................... 94
6.4 ExperimentalResults....................................... 95
6.5 Summary ................................................ 98
7 SummaryofOn-ChipCrosstalkAvoidance........................ 101
PartII Off-ChipCrosstalkandAvoidance........................... 105
8 IntroductiontoOff-ChipCrosstalk .............................. 107
8.1 TheRoleofICPackaging................................... 107
8.2 NoiseSourcesinPackaging ................................. 109
8.2.1 InductiveSupplyBounce ............................. 109
8.2.2 InductiveSignalCoupling ............................ 111
8.2.3 CapacitiveBandwidthLimiting........................ 113
8.2.4 CapacitiveSignalCoupling ........................... 114
8.2.5 ImpedanceDiscontinuities............................ 115
Contents xi
8.3 PerformanceModelingandProposedTechniques ............... 117
8.3.1 PerformanceModeling............................... 117
8.3.2 OptimalBusSizing.................................. 117
8.3.3 BusEncoding ...................................... 118
8.3.4 ImpedanceCompensation ............................ 119
8.4 AdvantagesOverPriorTechniques ........................... 120
8.4.1 PerformanceModeling............................... 120
8.4.2 OptimalBusSizing.................................. 121
8.4.3 BusEncoding ...................................... 122
8.4.4 ImpedanceCompensation ............................ 123
8.5 BroaderImpactofThisMonograph........................... 123
8.6 OrganizationofPartIIofthisMonograph ..................... 124
9 PackageConstructionandElectricalModeling .................... 125
9.1 Level1Interconnect ....................................... 125
9.1.1 WireBonding ...................................... 125
9.1.2 Flip-ChipBumping.................................. 127
9.2 Level2Interconnect ....................................... 129
9.2.1 LeadFrame ........................................ 129
9.2.2 ArrayPattern ....................................... 130
9.3 ModernPackages.......................................... 131
9.3.1 QuadFlatPackwithWireBonding..................... 132
9.3.2 BallGridArraywithWireBonding .................... 133
9.3.3 BallGridArraywithFlip-ChipBumping................ 134
9.4 ElectricalModeling ........................................ 135
9.4.1 QuadFlatPackwithWireBonding..................... 135
9.4.2 BallGridArraywithWireBonding .................... 135
9.4.3 BallGridArraywithFlip-ChipBumping................ 136
10 PreliminariesandTerminology .................................. 137
10.1 BusConstruction .......................................... 137
10.2 LogicValuesandTransitions ................................ 139
10.3 SignalCoupling ........................................... 140
10.3.1 MutualInductiveSignalCoupling ..................... 140
10.3.2 MutualCapacitiveSignalCoupling .................... 141
10.4 ReturnCurrent ............................................ 141
10.5 NoiseLimits.............................................. 142
11 AnalyticalModelforOff-ChipBusPerformance................... 145
11.1 PackagePerformanceMetrics ............................... 145
11.2 ConvertingPerformancetoRisetime.......................... 146
11.3 ConvertingBusPerformanceto di and dv...................... 147
dt dt
11.4 TranslatingNoiseLimitstoPerformance ...................... 148
11.4.1 InductiveSupplyBounce ............................. 148
11.4.2 CapacitiveBandwidthLimiting........................ 150
xii Contents
11.4.3 SignalCoupling..................................... 151
11.4.4 ImpedanceDiscontinuities............................ 152
11.5 ExperimentalResults....................................... 152
11.5.1 TestCircuit ........................................ 153
11.5.2 QuadFlatPackwithWireBondingResults.............. 154
11.5.3 BallGridArraywithWireBondingResults.............. 156
11.5.4 BallGridArraywithFlip-ChipBumpingResults......... 157
11.5.5 Discussion ......................................... 159
12 OptimalBusSizing............................................. 161
12.1 PackageCost ............................................. 161
12.2 BandwidthPerCost........................................ 163
12.2.1 ResultsforQuadFlatPackwithWireBonding........... 163
12.2.2 ResultsforBallGridArraywithWireBonding........... 164
12.2.3 ResultsforBallGridArraywithFlip-ChipBumping...... 164
12.3 BusSizingExample........................................ 166
13 BusExpansionEncoder......................................... 167
13.1 ConstraintEquations ....................................... 167
13.1.1 SupplyBounceConstraints ........................... 168
13.1.2 SignalCouplingConstraints .......................... 168
13.1.3 CapacitiveBandwidthLimitingConstraints ............. 170
13.1.4 ImpedanceDiscontinuityConstraints................... 171
13.1.5 NumberofConstraintEquations....................... 172
13.1.6 NumberofConstraintEvaluations ..................... 172
13.2 EncoderConstruction ...................................... 173
13.2.1 EncoderAlgorithm .................................. 173
13.2.2 EncoderOverhead................................... 175
13.3 DecoderConstruction ...................................... 175
13.4 ExperimentalResults....................................... 175
13.4.1 3-BitFixed di Example .............................. 176
dt
13.4.2 3-BitVarying di Example............................. 180
dt
13.4.3 FunctionalImplementation ........................... 182
13.4.4 PhysicalImplementation ............................. 183
13.4.5 MeasurementResults ................................ 185
14 BusStutteringEncoder ......................................... 189
14.1 EncoderConstruction ...................................... 189
14.1.1 EncoderAlgorithm .................................. 190
14.1.2 EncoderOverhead................................... 191
14.2 DecoderConstruction ...................................... 192
14.3 ExperimentalResults....................................... 192
14.3.1 FunctionalImplementation ........................... 194
14.3.2 PhysicalImplementation ............................. 196