Offset Reduction Techniques in High-Speed Analog-To-Digital Converters Analysis Design and Tradeoff

395 Pages·2009·10.25 MB·English

by  Pedro M. Figueiredo

OFFSET REDUCTION TECHNIQUES IN HIGH-
SPEED ANALOG-TO-DIGITAL CONVERTERS
Analysis, Design and Tradeoffs
ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES
Consulting Editor: Mohammed Ismail. Ohio State University
For other titles published in this series, go to
www.springer.com/series/7381
OFFSET REDUCTION TECHNIQUES IN HIGH-
SPEED ANALOG-TO-DIGITAL CONVERTERS
Analysis, Design and Tradeoffs

PEDRO M. FIGUEIREDO
MIPSABG Chipidea
JOÃO C. VITAL
MIPSABG Chipidea
Pedro M. Figueiredo João C. Vital
Chipidea Microeletrónica Chipidea Microeletrónica
Av. Dr. Mário Soares 33 Av. Dr. Mário Soares 33
2740-119 Porto-Salvo 2740-119 Porto-Salvo
Taguspark, Portugal Taguspark, Portugal
[e-mail] [e-mail]
ISBN: 978-1-4020-9715-7 e-ISBN: 978-1-4020-9716-4
Library of Congress Control Number: 2008942088
©Springer Science+Business Media B.V. 2009
No part of the work may be reproduced, stored in a retrieval system, or transmitted in any form or by
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Printed on acid-free paper.
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To Patrícia and Gonçalo
Contents
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .xv
1. HIGH-SPEED ADC ARCHITECTURES . . . . . . . . . . . . . . . .1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 The Analog-to-Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . .2
1.2.1 Basic Operations and Transfer Function . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Static Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Dynamic Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3.1 Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.2 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 10
1.3.3 The Interpolation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Two-Step Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4.1 Two-Step Flash ADC with DAC and Subtractor . . . . . . . . . . . . . . 17
1.4.2 Two-Step Subranging Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Folding and Interpolation ADCs. . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.1 Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.2 Cascaded Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.3 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 33
1.6 Building Blocks of CMOS High-Speed ADCs . . . . . . . . . . . . . . . .38
1.6.1 The MOS Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.6.2 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.6.3 CMOS Folding Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.6.4 Latched Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
1.6.5 Considerations About the Yield . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2. AVERAGING TECHNIQUE – DC ANALYSIS AND
TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
vii
viii Offset Reduction Techniques in High-Speed ADCs
2.2 Published Studies on the Averaging Technique. . . . . . . . . . . . . . .73
2.3 Output Voltage and Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.3.1 Equivalent Resistance of an Infinite Resistive Network . . . . . . . . . . 76
2.3.2 Calculation of the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.3 Calculation of the Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.4 Application to MOS Differential Pairs . . . . . . . . . . . . . . . . . . . . . . 81
2.4 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . . .86
2.4.1 INL due to Mismatches in the Transistors and Current Sources . . . 87
2.4.2 DNL due to Mismatches in the Transistors and Current Sources . . . 89
2.4.3 Mismatches in the Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.4.4 Application to MOS Differential Pairs . . . . . . . . . . . . . . . . . . . . . . 90
2.5 Averaging in Folding Circuits. . . . . . . . . . . . . . . . . . . . . . . . . .103
2.5.1 Output Voltage and Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.5.2 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . . . 111
2.6 Considerations About the Yield . . . . . . . . . . . . . . . . . . . . . . . .116
2.7 Termination of the Averaging Network . . . . . . . . . . . . . . . . . . .118
2.7.1 Existing Terminating Strategies . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.7.2 Improved Terminating Strategy . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.7.3 Comparison of the Terminating Solutions . . . . . . . . . . . . . . . . . . 132
2.7.4 Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
3. AVERAGING TECHNIQUE – TRANSIENT ANALYSIS AND
AUTOMATED DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
3.2 Flash ADC Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
3.3 Output Voltage and Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
3.3.1 Exact Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.3.2 Approximated Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
3.4 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
3.4.1 Simulation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.4.2 Time Dependence of the Offset Voltage . . . . . . . . . . . . . . . . . . . . 160
3.5 Design of Averaged Pre-amplifier Stages in Flash ADCs . . . . . . .169
3.5.1 Interface with HSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
3.5.2 Properties of Differential Pairs with the Same Saturation Voltage
(V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
SAT
3.5.3 Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3.5.4 Application Example: Pre-amplifier Stage for a 7-bit 200 MS/s Flash
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3.5.5 Application Example: Variation of G . . . . . . . . . . . . . . . . . . . . . 181
0
3.5.6 Application Example: Variation of α . . . . . . . . . . . . . . . . . . . . . . 185
3.5.7 Application Example: Variation of N . . . . . . . . . . . . . . . . . . . . . 187
3.5.8 Application Example: Variation of R /R . . . . . . . . . . . . . . . . . . 191
0 1
3.5.9 Application Example: Variation of f . . . . . . . . . . . . . . . . . . . . . . 193
s
3.5.10 Application Example: Specifying the I R Product . . . . . . . . . . . 196
SS 0
3.5.11 Application Example: Interpolation in Averaged Pre-amplifiers . . . 200
Contents ix
4. INTEGRATED PROTOTYPES USING AVERAGING . . . 205
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
4.2 7-bit 120 MS/s I/Q Flash ADC. . . . . . . . . . . . . . . . . . . . . . . . .206
4.2.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
4.2.2 Bias Current Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
4.2.3 Pre-amplifier Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
4.2.4 Resistive Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
4.2.5 Reference Voltage Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
4.2.6 Latched Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
4.2.7 Digital Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
4.2.8 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 222
4.3 10-bit 100 MS/s Folding and Interpolation ADC . . . . . . . . . . . .227
4.3.1 Specifications and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 227
4.3.2 Sample-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
4.3.3 Folding Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
4.3.4 Latched Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
4.3.5 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 246
5. OFFSET CANCELLATION METHODS . . . . . . . . . . . . . . 261
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
5.2 Offset Cancellation Techniques. . . . . . . . . . . . . . . . . . . . . . . . .262
5.2.1 Input Offset Storage (IOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.2.2 Output Offset Storage (OOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.2.3 Multi-stage Offset Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
5.2.4 Utilization of Auxiliary Differential Pairs . . . . . . . . . . . . . . . . . . 271
5.3 New Offset Cancellation Technique. . . . . . . . . . . . . . . . . . . . . .273
5.3.1 Offset Calibration in the Pre-amplifier and Latched Comparator . . 274
5.3.2 Elimination of Charge Injection Differences . . . . . . . . . . . . . . . . . 281
5.4 6-bit 1 GHz Two-Step Subranging ADC . . . . . . . . . . . . . . . . . .285
5.4.1 Specifications and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 285
5.4.2 Fine Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
5.4.3 Coarse Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
5.4.4 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
5.4.5 Selection of the Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . 296
5.4.6 Layout and Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 300
CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
6.
6.1 Overview of the Research Work . . . . . . . . . . . . . . . . . . . . . . . .305
Appendix A. AVERAGING WITH PIECEWISE LINEAR
DIFFERENTIAL PAIRS . . . . . . . . . . . . . . . . . . . . . . . . . 313
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
A.2 Output Voltage and Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
A.3 Effect of Mismatches – INL and DNL . . . . . . . . . . . . . . . . . . . .318
x Offset Reduction Techniques in High-Speed ADCs
A.3.1 Mismatches in the Transistors of the Differential Pair . . . . . . . . . 319
A.3.2 Mismatches in the Tail Current Sources . . . . . . . . . . . . . . . . . . . 323
A.3.3 Mismatches in Resistors R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
0
A.3.4 Mismatches in Resistors R . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
1
Appendix B. MISMATCHES IN THE RESISTORS OF THE
AVERAGING NETWORK . . . . . . . . . . . . . . . . . . . . . . . . 333
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
B.2 Mismatches in Resistors R . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
0
B.3 Mismatches in Resistors R . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
1
B.3.1 Common-Mode Mismatch Component (δR [k]) . . . . . . . . . . . . . . . 336
1
B.3.2 Differential-Mode Mismatch Component (ΔR [k]) . . . . . . . . . . . . 339
1
Appendix C. AVERAGING IN FOLDING STAGES . . . . . . . . . . 341
C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
C.2 Equivalence Between Circular and Infinite Networks . . . . . . . . .345
C.3 Output Voltage and Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
C.3.1 Calculation of the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . 348
C.3.2 Calculation of the Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
C.4 Effect of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
C.4.1 INL due to Mismatches in the Transistors and Current Sources . . 355
C.4.2 DNL due to Mismatches in the Transistors and Current Sources . . 357
C.4.3 INL and DNL due to Mismatches in the Resistors . . . . . . . . . . . . 359
REFERENCES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379