Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC

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ADS5294
SLAS776E–NOVEMBER2011–REVISEDAPRIL2018
ADS5294 Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC
1 Features 3 Description
• MaximumSampleRate:80MSPS/14-Bit The ADS5294 is a low-power 80-MSPS 8-Channel
1 ADC that uses CMOS process technology and
• HighSignal-to-NoiseRatio
innovative circuit techniques. Low power
– 75.5-dBFSSNRat5MHz/80MSPS consumption, high SNR, low SFDR, and consistent
– 78.2-dBFSSNRat5MHz/80MSPSand overload recovery allow users to design high-
DecimationFilterEnabled performancesystems.
– 84-dBcSFDRat5MHz/80MSPS The digital processing block of the ADS5294
integrates several commonly used digital functions for
• LowPowerConsumption
improving system performance. The device includes
– 58mW/CHat50MSPS
a digital filter module that has built-in decimation
– 77mW/CHat80MSPS(2-LVDSWirePer filters (with lowpass, highpass and bandpass
Channel) characteristics). The decimation rate is also
programmable(by2,by4,orby8). Thisrate isuseful
• DigitalProcessingBlock
for narrow-band applications, where the filters are
– ProgrammableFIRDecimationFilterand
used to conveniently improve SNR and knock-off
OversamplingtoMinimizeHarmonic harmonics, while at the same time reducing the
Interference output data rate. The device includes an averaging
– ProgrammableIIRHigh-PassFiltertoMinimize mode where two channels (or even four channels)
DCOffset areaveragedtoimproveSNR.
– ProgrammableDigital Gain:0dBto12dB
DeviceInformation(1)
– 2-Channelor4-ChannelAveraging
PARTNUMBER PACKAGE BODYSIZE(NOM)
• FlexibleSerializedLVDSOutputs:
ADS5294 HTQFP(80) 12.00mm×12.00mm
– OneorTwoWiresofLVDSOutputLinesPer
(1) For all available packages, see the orderable addendum at
ChannelDependingonADCSamplingRate theendofthedatasheet.
– ProgrammableMappingBetweenADCInput
SimplifiedBlockDiagram
ChannelsandLVDSOutputPins-EasesBoard
– VDaersieigtnyof TestPatternstoVerifyDataCapture AVDD AGND LVDD LGND
1 of 8 Channels
byFPGA/Receiver OUTxA_P
• InternalandExternalReferences IINNxxNP SCAIMRPCLUINITG 14 BITA1 A4DD AbCiCt DIGITALB PLROOCCKESSING SERIALIZER OOUUTTxxAB__NP
OUTxB_N
• 1.8-VOperationforLowPowerConsumption
LCLKP
• Low-FrequencyNoiseSuppression CLKP CLOCKGEN LCLKN
CLKN PLL
• RecoveryFrom6-dBOverloadWithin1Clock SYNC AACCLLKKNP
Cycle
REFERENCE CONTROL
• Package:12-mm ×12-mm80-PinQFP INTERFACE ADS5294
2 Applications REFT REFB VCM PD RESETSCLK CSZSDATA SDOUT
• UltrasoundandSonarImaging
• CommunicationApplications
• Multi-channelDataAcquisition
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
ADS5294
SLAS776E–NOVEMBER2011–REVISEDAPRIL2018 www.ti.com
Table of Contents
1 Features.................................................................. 1 FilterEnabled..........................................................16
2 Applications........................................................... 1 8.14 LVDSTimingatDifferentSamplingFrequencies—
1-WireInterface,14x-Serialization,Decimationby8
3 Description............................................................. 1
FilterEnabled..........................................................16
4 RevisionHistory..................................................... 2
8.15 TypicalCharacteristics..........................................22
5 Description(continued)......................................... 5 9 DetailedDescription............................................ 28
6 DeviceComparisonTable..................................... 6 9.1 Overview.................................................................28
7 PinConfigurationandFunctions......................... 7 9.2 FunctionalBlockDiagram.......................................29
8 Specifications......................................................... 9 9.3 FeatureDescription.................................................30
8.1 AbsoluteMaximumRatings......................................9 9.4 DeviceFunctionalModes........................................37
8.2 ESDRatings..............................................................9 9.5 Programming...........................................................37
8.3 RecommendedOperatingConditions.....................10 9.6 RegisterMaps.........................................................40
8.4 ThermalInformation................................................10 10 ApplicationandImplementation........................ 64
8.5 ElectricalCharacteristicsDynamicPerformance....11 10.1 ApplicationInformation..........................................64
8.6 DigitalCharacteristics.............................................12 10.2 TypicalApplication ...............................................65
8.7 TimingRequirements..............................................13 11 PowerSupplyRecommendations..................... 69
8.8 LVDSTimingatDifferentSamplingFrequencies— 12 Layout................................................................... 69
2-WireInterface,7x-Serialization,DigitalFilter
12.1 LayoutGuidelines.................................................69
Disabled ..................................................................14
12.2 LayoutExample....................................................70
8.9 LVDSTimingatDifferentSamplingFrequencies—
1-WireInterface,14x-Serialization,DigitalFilter 13 DeviceandDocumentationSupport................. 71
Disabled ..................................................................14 13.1 DeviceSupport......................................................71
8.10 SerialInterfaceTimingRequirements...................15 13.2 DocumentationSupport........................................73
8.11 ResetTiming.........................................................15 13.3 CommunityResources..........................................73
8.12 LVDSTimingatDifferentSamplingFrequencies— 13.4 Trademarks...........................................................73
1-WireInterface,14x-Serialization,Decimationby2
13.5 ElectrostaticDischargeCaution............................73
FilterEnabled..........................................................16
13.6 Glossary................................................................73
8.13 LVDSTimingatDifferentSamplingFrequencies—
1-WireInterface,14x-Serialization,Decimationby4 14 Mechanical,Packaging,andOrderable
Information........................................................... 73
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionD(September2015)toRevisionE Page
• AddedThemaximumlimitusedfortheLVDDcurrentat–40°Cis132mAtablenote....................................................... 12
• AddedbypassdecimationvaluestotheDATA_RATE,FILTERn_RATE,andFILTERn_COEFF_SETcolumns............... 33
• ChangedD15valueofADDR.(HEX)28toX...................................................................................................................... 41
• Changedthistothebyte-wiseforclarification...................................................................................................................... 41
• Changedthistotheword-wiseforclarification..................................................................................................................... 41
• ChangedD15valueto1inBit-Byte-WordWiseOutputtable.............................................................................................. 48
• AddedDATA_RATE>,FILTERn_RATE,andFILTERn_COEFF_SETvaluestothebypassdecimationrowinthe
DigitalFilterstable................................................................................................................................................................ 55
ChangesfromRevisionC(September2013)toRevisionD Page
• AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional
Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device
andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1
• Added"SonarImaging"inApplications ................................................................................................................................. 1
• UpdatedPinout....................................................................................................................................................................... 7
• Addedtextnote2toFigure1 .............................................................................................................................................. 17
• AddedatextnotetoFigure44. ........................................................................................................................................... 30
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• CorrectedtypoinTable1..................................................................................................................................................... 33
• AddednotetoEN_2WIREbit............................................................................................................................................... 44
• CorrectedtypoinTable17................................................................................................................................................... 55
ChangesfromRevisionB(July2012)toRevisionC Page
• Addedcross-referencelinkforVCMpin................................................................................................................................. 7
• AddednoteforREFBpinunderINT/EXTreferencemodes.................................................................................................. 8
• AddednoteforREFTpinunderINT/EXTreferencemodes.................................................................................................. 8
• ChangedthemaximumratingofdigitalinputpinsRESET,SCLK,SDATA,SYNC,PD,CSZto3.6V.................................. 9
• Addedtestcondition"DigitalFilterDisabled"andchanged"LVDSoutputrate"to"ADCCLKFrequency"inLVDS
TimingatDifferentSamplingFrequencies—2-WireInterface,7x-Serialization,DigitalFilterDisabled............................ 14
• Addedtestcondition"DigitalFilterDisabled"andchanged"LVDSoutputrate"to"ADCCLKFrequency"inLVDS
TimingatDifferentSamplingFrequencies—1-WireInterface,14x-Serialization,DigitalFilterDisabled.......................... 14
• AddednoteafterLVDSTimingatDifferentSamplingFrequencies—1-WireInterface,14x-Serialization,Digital
FilterDisabled:TheaboveLVDStimingspecisonlyvalidwhendigitalfiltersaredisabled.............................................. 14
• AddedLVDSTimingatDifferentSamplingFrequencies—1-WireInterface,14x-Serialization,Decimationby2Filter
Enabled................................................................................................................................................................................ 16
• AddedLVDSTimingatDifferentSamplingFrequencies—1-WireInterface,14x-Serialization,Decimationby4Filter
Enabled................................................................................................................................................................................ 16
• AddedLVDSTimingatDifferentSamplingFrequencies—1-WireInterface,14x-Serialization,Decimationby8Filter
Enabled................................................................................................................................................................................ 16
• AddedanoterelatedtoEN_CUSTOM_FILTandchangedformatsinTable9................................................................... 33
• AddedPLLOperationVersusLVDSTimingbeforeAPPLICATIONINFORMATIONsection ............................................ 35
• AddedanotelinktoReg.0x38............................................................................................................................................ 44
• Changed0xF[15]to0xF0[15]inthedescriptionofReg.0x42.............................................................................................. 44
• ChangedtheReg.0x46[11:8]formatting.............................................................................................................................. 44
• CorrectedtheEN_RAMPaddressfrom0x24to0x25inthesectionofLVDStestpatterns. ............................................. 47
• Changed"NotethatthesebitsarefunctionalonlywhentheGLOBAL_EN_FILTERgetssetto1"to"Notethatthese
bitsarefunctionalonlywhentheGLOBAL_EN_FILTERgetssetto1andUSE_FILTERnbitissetto1”inthe
sectionofDecimationFilter,. ............................................................................................................................................... 54
• AddedanoterelatedtoEN_CUSTOM_FILTandchangedformatsinTable17................................................................. 55
• ChangedEquation(5).......................................................................................................................................................... 59
• AddedregisteraddressinTable23..................................................................................................................................... 59
• RevisedFigure63andmovedthe2pFcaptothelefthandsideoftheresistors............................................................... 66
• AddedanoteregardingthelocationofLVDSRterminthesectionofInputclock. ............................................................ 67
ChangesfromRevisionA(November2011)toRevisionB Page
• ChangedthelocationofOUTAandOUTBinFigure5andFigure6................................................................................. 20
• AddedFigure45................................................................................................................................................................... 31
• ReplacedTable9(DecimationFilterModes)withnewTable1-DigitalFilters................................................................... 33
• Deletedsection:SynchronizationPulse............................................................................................................................... 35
• AddedEN_HIGH_ADDRStoTable3................................................................................................................................... 40
• MovedEN_EXT_REFFrom:0x0FTo:0xF0inTable3....................................................................................................... 45
• AddedthesectionBIT-BYTE-WORDWISEOUTPUT.AddedFigure53andFigure54..................................................... 48
• AddedsectionDIGITALPROCESSINGBLOCKS............................................................................................................... 49
• ReplacedTable5andTable6withnewTable17-DigitalFilters....................................................................................... 55
• ChangedtheSYNCHRONIZATIONPULSEsection............................................................................................................ 58
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• AddedtheExternalReferenceModeofOperationsection.................................................................................................. 59
ChangesfromOriginal(November2011)toRevisionA Page
• ChangedFrom:ProductPreviewTo:Production................................................................................................................... 1
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5 Description (continued)
Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The digital
data from each channel ADC is output over one or two wires of LVDS output lines depending on the ADC
sampling rate. This 2-wire interface maintains a low serial-data rate, allowing low-cost FPGA-based receivers to
be used even at a high sample rate. The ADC resolution is programmed to 12-bit or 14-bit through registers. A
unique feature is the programmable-mapping module that allows flexible mapping between the input channels
and the LVDS output pins. This module greatly reduces the complexity of LVDS-output routing, and by reducing
thenumberofPCBlayers,potentiallyresultsincheapersystem boards.
The device integrates an internal reference trimmed to accurately match across devices. Internal reference mode
achievesthebestperformance.Externalreferencescanalsodrivethedevice.
The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specified over a –40°C to 85°C
operatingtemperaturerange.ADS5294iscompletelypin-to-pinandregistercompatibletoADS5292.
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6 Device Comparison Table
DEVICE DESCRIPTION PACKAGE BODYSIZE(NOM)
ADS5294 Octal-channel,14-bit,80-MSPSADC,75-dBFSSNR,77mW/ch HTQFP(80) 14.00mm×14.00mm
ADS5292 Octal-channel,12-bit,80-MSPSADC,70-dBFSSNR,66mW/ch HTQFP(80) 14.00mm×14.00mm
ADS5295 Octal-channel,12-bit,100-MSPSADC,70.6-dBFSSNR,80mW/ch HTQFP(80) 14.00mm×14.00mm
10-bit,200-MSPS,4-channel,61-dBFSSNR,150-mW/chand12-bit,80-MSPS,
ADS5296A VQFN(64) 9.00mm×9.00mm
8-channel,70-dBFSSNR,65-mW/chADC
8-channelvariable-gainamplifier(VGA)withoctalhigh-speedADC,5.5nV/√Hz,
AFE5801 VQFN(64) 9.00mm×9.00mm
12bits,65MSPS,65mW/ch
AFE5803 8-channelAFE,0.75nV/√Hz,14and12bits,65MSPS,158mW/ch NFBGA(135) 15.00mm×9.00mm
AFE5804 8-channelAFE,1.23nV/√Hz,12bits,50MSPS,101mW/ch NFBGA(135) 15.00mm×9.00mm
AFE5805 8-channelAFE,0.85nV/√Hz,12bits,50MSPS,122mW/ch NFBGA(135) 15.00mm×9.00mm
AFE5807 8-channelAFEwithpassiveCWmixer,1.05nV/√Hz,12bits,80MSPS,117mW/ch NFBGA(135) 15.00mm×9.00mm
8-channelAFEwithpassiveCWmixer,0.75nV/√Hz,14and12bits,
AFE5808A NFBGA(135) 15.00mm×9.00mm
65MSPS,158mW/ch
8-channelAFEwithpassiveCWmixer,anddigitalI/Qdemodulator,
AFE5809 NFBGA(135) 15.00mm×9.00mm
0.75nV/√Hz,14and12bits,65MSPS,158mW/ch
Fullyintegrated,8-channelAFEwithpassiveCWmixer,anddigitalI/Qdemodulator,
AFE5812 NFBGA(135) 15.00mm×9.00mm
0.75nV/√Hz,14and12bits,65MSPS,180mW/ch
16-ChannelAFEwith124-mW/Channel,0.75-nV/√HzNoise,14-Bit,65-MSPSor12-
AFE5818 NFBGA(289) 15.00mm×15.00mm
Bit,80-MSPSADC,andPassiveCWMixer
16-channelAFEwith90-mW/channel,1-nV/√Hznoise,14-bit,65-MSPSor12-bit,80-
AFE5816 NFBGA(289) 15.00mm×15.00mm
MSPSADCandpassiveCWmixer
AFE5851 16-channelVGAwithhigh-speedADC,5.5nV/√Hz,12bits,32.5MSPS,39mW/ch VQFN(64) 9.00mm×9.00mm
VCA8500 8-channel,ultralow-powerVGAwithlow-noisepre-amp,0.8nV/√Hz,65mW/ch VQFN(64) 9.00mm×9.00mm
8-channelvoltage-controlledamplifierwithpassiveCWmixer,
VCA5807 HTQFP(80) 14.00mm×14.00mm
0.75nV/√Hz,99mW/ch
PGA5807A Integrated8-channelAFEwithLNA,PGA,andLPF,2.1nV/√Hz,60mW/ch VQFN(64) 9.00mm×9.00mm
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7 Pin Configuration and Functions
PFPPackage
80-PINTQFPWithThermalPad
TopView
AGND IN1N IN1P SCLK SDATA CSZ AVDD CLKN CLKP AVDD REFT REFB VCM NC AVDD SYNC SDOUT IN8N IN8P AGND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
IN2P 1 60 IN7N
IN2N 2 59 IN7P
AGND 3 Thermal Pad 58 AGND
IN3P 4 (Can be tied to AGND) 57 IN6N
IN3N 5 56 IN6P
AGND 6 55 AGND
IN4P 7 54 IN5N
IN4N 8 53 IN5P
AVDD 9 52 AVDD
PD 10 ADS529X 51 RESET
80 TQFP
LVDD 11 50 LGND
LGND 12 49 LVDD
OUT1A_P 13 48 OUT8A_N
OUT1A_N 14 47 OUT8A_P
OUT1B_P 15 46 OUT8B_N
OUT1B_N 16 45 OUT8B_P
OUT2A_P 17 44 OUT7A_N
OUT2A_N 18 43 OUT7A_P
OUT2B_P 19 42 OUT7B_N
OUT2B_N 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041 OUT7B_P
OUT3A_P OUT3A_N OUT3B_P OUT3B_N OUT4A_P OUT4A_N OUT4B_P OUT4B_N ACLKP ACLKN LCLKP LCLKN OUT5B_P OUT5B_N OUT5A_P OUT5A_N OUT6B_P OUT6B_N OUT6A_P OUT6A_N
PinFunctions
PIN
DESCRIPTION
NAME NO.
AVDD 9,52,66,71,74 Analogpowersupply,1.8V
AGND 3,6,55,58,61,80 Analogground
Common-modeoutputpin,0.95-Voutput.Thispincanbeconfiguredastheexternalreferencevoltage(1.5
VCM 68
V)inputpinaswell.SeeReg0x42andExternalReferenceModeofOperation.
CLKN 73 Negativedifferentialclock–TieCLKNtoGNDforsingle-endedclock
CLKP 72 Positivedifferentialclock
IN1P,IN1N 78,79 Differentialinputsignal,Channel1
IN2P,IN2N 1,2 Differentialinputsignal,Channel2
IN3P,IN3N 4,5 Differentialinputsignal,Channel3
IN4P,IN4N 7,8 Differentialinputsignal,Channel4
IN5P,IN5N 53,54 Differentialinputsignal,Channel5
IN6P,IN6N 56,57 Differentialinputsignal,Channel6
IN7P,IN7N 59,60 Differentialinputsignal,Channel7
IN8P,IN8N 62,63 Differentialinputsignal,Channel8
LCLKP,LCLKN 31,32 DifferentialLVDSbitclock(7X)
ACLKP,ACLKN 29,30 DifferentialLVDSframeclock(1X)
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PinFunctions (continued)
PIN
DESCRIPTION
NAME NO.
OUT1A_P,OUT1A_N 13,14 DifferentialLVDSdataoutput,wire1,channel1
OUT1B_P,OUT1B_N 15,16 DifferentialLVDSdataoutput,wire2,channel1
OUT2A_P,OUT2A_N 17,18 DifferentialLVDSdataoutput,wire1,channel2
OUT2B_P,OUT2B_N 19,20 DifferentialLVDSdataoutput,wire2,channel2
OUT3A_P,OUT3A_N 21,22 DifferentialLVDSdataoutput,wire1,channel3
OUT3B_P,OUT3B_N 23,24 DifferentialLVDSdataoutput,wire2,channel3
OUT4A_P,OUT4A_N 25,26 DifferentialLVDSdataoutput,wire1,channel4
OUT4B_P,OUT4B_N 27,28 DifferentialLVDSdataoutput,wire2,channel4
OUT5A_P,OUT5A_N 35,36 DifferentialLVDSdataoutput,wire1,channel5
OUT5B_P,OUT5B_N 33,34 DifferentialLVDSdataoutput,wire2,channel5
OUT6A_P,OUT6A_N 39,40 DifferentialLVDSdataoutput,wire1,channel6
OUT6B_P,OUT6B_N 37,38 DifferentialLVDSdataoutput,wire2,channel6
OUT7A_P,OUT7A_N 43,44 DifferentialLVDSdataoutput,wire1,channel7
OUT7B_P,OUT7B_N 41,42 DifferentialLVDSdataoutput,wire2,channel7
OUT8A_P,OUT8A_N 47,48 DifferentialLVDSdataoutput,wire1,channel8
OUT8B_P,OUT8B_N 45,46 DifferentialLVDSdataoutput,wire2,channel8
PD 10 Power-downcontrolinput.ActiveHigh.Thepinhasaninternal220-kΩpulldownresistor.
Negativereferenceinputandoutput.Internalreferencemode:Referencebottomvoltage(0.45V)isoutput
REFB 69 onthispin.Adecouplingcapacitorisnotrequiredonthispin.Externalreferencemode:Referencebottom
voltage(0.45V)mustbeexternallyappliedtothispin.PleaseseeExternalReferenceModeofOperation.
Positivereferenceinputandoutput.Internalreferencemode:Referencetopvoltage(1.45V)isoutputonthis
REFT 70 pin.Adecouplingcapacitorisnotrequiredonthispin.Externalreferencemode:Referencetopvoltage(1.45
V)mustbeexternallyappliedtothispin.PleaseseeExternalReferenceModeofOperation.
RESET 51 ActiveHIGHRESETinput.Thepinhasaninternal220-kΩpulldownresistor.
SCLK 77 Serialclockinput.Thepinhasaninternal220-kΩpulldownresistor.
SDATA 76 Serialdatainput.Thepinhasaninternal220-kΩpulldownresistor.
Serialdatareadout.Thispinisinthehigh-impedancestateafterreset.Whenthe<READOUT>bitisset,the
SDOUT 64
SDOUTpinbecomesactive.SDOUTisaCMOSdigitaloutputrunningfromtheAVDDsupply.
CSZ 75 Serialenablechipselect–active-lowdigitalinput
Inputsignaltosynchronizechannelsandchipswhenusedwithreducedoutputdatarates.Ifitisnotused,
SYNC 65
adda≤10-KΩpulldownresistor.
LVDD 11,49 DigitalandI/Opowersupply,1.8V
LGND 12,50 Digitalground
NC 67 NoConnection.Mustleavefloated
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8 Specifications
8.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1)
MIN MAX UNIT
AVDD –0.3 2.2 V
Supplyvoltage
LVDD –0.3 2.2 V
BetweenAGNDandLGND –0.3 0.3 V
Atanaloginputs min[2.2,
–0.3 V
AVDD+0.3]
Atdigitalinputs,RESET,SCLK,SDATA,SYNC,PD,CSZ –0.3 3.6 V
Voltage
AtCLKN,CLKP(2), min[2.2,
–0.3 V
AVDD+0.3]
Atdigitaloutputs min[2.2,
–0.3 V
LVDD+0.3]
Maximumjunctiontemperature(T ),anycondition 105 °C
J
Operatingtemperature –40 85 °C
Storagetemperature,T –55 150 °C
stg
(1) Stressesabovethoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmaydegradedevicereliability.
(2) WhenAVDDisturnedoff,TIrecommendstoswitchofftheinputclock(orensurethevoltageonCLKP,CLKNis<|0.3V|).Thisprevents
theESDprotectiondiodesattheclockinputpinsfromturningon.
8.2 ESD Ratings
VALUE UNIT
Electrostatic Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000
V V
(ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±250
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
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8.3 Recommended Operating Conditions
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 1.7 1.8 1.9 V
LVDD Digitalsupplyvoltage 1.7 1.8 1.9 V
ANALOGINPUTS/OUTPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 0.95±0.05 V
REF Externalreferencemode 1.45 V
T
REF Externalreferencemode 0.45 V
B
Common-modevoltageoutput 0.95 V
VCM
ExternalReferencemodeInput 1.5 V
MaximumInputFrequency (1) 2V amplitude 80 MHz
PP
CLOCKINPUTS
ADCClockinputsamplerate 10 80 MSPS
Sinewave,AC-coupled 0.2 1.5
InputClockamplitudedifferential
LVPECL,AC-coupled 0.2 1.6 V
(V –V )peak-to-peak PP
(CLKP) (CLKN)
LVDS,AC-coupled 0.2 0.7
V <0.3 V
IL
InputClockCMOSsingle-ended(V )
(CLKP)
V >1.5 V
IH
Inputclockdutycycle 35% 50% 65%
DIGITALOUTPUTS
ACLKPandACLKNoutputs(LVDS),1-wireinterface 1x(samplerate) MSPS
LCLKPandLCLKNoutputs(LVDS),1-wireinterface 7x(samplerate) MSPS
ACLKPandACLKNoutputs(LVDS),2-wireinterface 0.5x(samplerate) MSPS
LCLKPandLCLKNoutputs(LVDS),2-wireinterface 3.5x(samplerate) MSPS
Maximumdatarate,2-wireinterface 560 Mbps
Maximumdatarate,1-wireinterface 700 Mbps
C MaximumexternalcapacitancefromeachoutputpintoLGND 5 pF
LOAD
R DifferentialloadresistancebetweentheLVDSoutputpairs 100 Ω
LOAD
T Operatingfree-airtemperature –40 85 °C
A
(1) SeetheLargeandSmallSignalInputBandwidthsection.
8.4 Thermal Information
ADS5294
THERMALMETRIC(1) PFP(HTQFP) UNIT
80PINS
R Junction-to-ambientthermalresistance 30.8 °C/W
θJA
R Junction-to-case(top)thermalresistance 6.3 °C/W
θJC(top)
R Junction-to-boardthermalresistance 8.3 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 0.2 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 8.2 °C/W
JB
R Junction-to-case(bottom)thermalresistance 0.3 °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report,SPRA953.
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