Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet PDF
Preview Octal Channel 12-Bit, 80 MSPS and Low-Power ADC datasheet
ADS5292 www.ti.com SLAS788B–NOVEMBER2011–REVISEDJULY2012 Octal Channel 12-Bit, 80 MSPS and Low-Power ADC CheckforSamples:ADS5292 FEATURES DESCRIPTION 1 • MaximumSampleRate:80MSPS/12-Bit Using CMOS process technology and innovative circuit techniques, the ADS5292 is a low power • HighSignal-to-NoiseRatio 80MSPS 8-Channel ADC. Low power consumption, – 70-dBFSSNRat5MHz/80MSPS high SNR, low SFDR, and consistent overload – 71.5-dBFS SNR at5MHz/80MSPSand recovery allow users to design high performance DecimationFilter=2 systems. – 85-dBcSFDRat5MHz/80MSPS The ADS5292 has a digital processing block that integrates several commonly used digital functions for • LowPowerConsumption improving system performance. It includes a digital – 48mW/CHat50MSPS filter module that has built-in decimation filters (with – 54mW/CHat65MSPS low-pass, high-pass and band-pass characteristics). – 66mW/CHat80MSPS(2LVDS WirePer The decimation rate is also programmable (by 2, by 4, or by 8). This makes it useful for narrow-band Channel) applications, where the filters can be used • DigitalProcessingBlock conveniently to improve SNR and knock-off – ProgrammableFIR DecimationFilterand harmonics, while at the same time reducing the OversamplingtoMinimizeHarmonic output data rate. The device includes an averaging Interference mode where two channels (or even four channels) canbeaveragedtoimproveSNR. – ProgrammableIIRHighPassFilterto MinimizeDCOffset Serial LVDS outputs reduce the number of interface lines and enable the highest system integration. The – ProgrammableDigitalGain:0dBto12dB digital data from each channel ADC can be output – 2-or4-ChannelAveraging over one or two wires of LVDS output lines • FlexibleSerializedLVDS Outputs: depending on the ADC sampling rate. This 2-wire – OneorTwowiresofLVDS OutputLinesper interface helps keep the serial data rate low, allowing low cost FPGA based receivers to be used even at ChannelDependingonADCSamplingRate high sample rate. A unique feature is the – ProgrammableMappingBetweenADC programmable mapping module that allows flexible InputChannelsand LVDSOutputPins- mapping between the input channels and the LVDS EasesBoardDesign output pins. This helps greatly reduce the complexity – VarietyofTestPatternstoVerifyData of LVDS output routing and can potentially result in CapturebyFPGA/Receiver cheaper system boards by reducing the number of PCBlayers. • InternalandExternalReferences The device integrates an internal reference trimmed • 1.8VOperationfor LowPowerConsumption to accurately match across devices. Best • Low-FrequencyNoiseSuppression performance is expected to be achieved through the • RecoveryFrom 6-dBOverloadwithin1Clock internal reference mode. The device can be driven Cycle withexternalreferencesaswell. • Package:12-mm×12-mm80-PinQFP The device is available in a 12 mm × 12 mm 80-pin QFP. It is specified over a –40°C to 85°C operating APPLICATIONS temperature range. ADS5292 is completely pin-to-pin andregistercompatibletoADS5294. • UltrasoundImaging • CommunicationApplications • Multi-channelDataAcquisition 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2011–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters. ADS5292 SLAS788B–NOVEMBER2011–REVISEDJULY2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12 BITADC 1122 BBIITTAADDCC 12 BITADC 12 BITADC 12 BITADC 12 BITADC 12 BITADC 12 BITADC Figure 1. BlockDiagram 2 SubmitDocumentationFeedback Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):ADS5292 ADS5292 www.ti.com SLAS788B–NOVEMBER2011–REVISEDJULY2012 PIN CONFIGURATION 80-PINTQFPWITHTHERMALPAD PFPPACKAGE(TOPVIEW) AGND IN1n IN1p SCLK SDATA CSZ AVDD CLKn CLKp AVDD REFT REFB VCM NC AVDD SYNC SDOUT IN8n IN8p AGND IN2p 180 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6160 IN7n IN2n 2 59 IN7p AGND 3 Thermal Pad 58 AGND IN3p 4 57 IN6n IN3n 5 56 IN6p AGND 6 55 AGND IN4p 7 54 IN5n IN4n 8 53 IN5p AVDD 9 52 AVDD PD 10 ADS529X 51 RESET 80TQFP LVDD 11 50 LGND LGND 12 49 LVDD OUT1A_p 13 48 OUT8A_n OUT1A_n 14 47 OUT8A_p OUT1B_p 15 46 OUT8B_n OUT1B_n 16 45 OUT8B_p OUT2A_p 17 44 OUT7A_n OUT2A_n 18 43 OUT7A_p OUT2B_p 19 42 OUT7B_n OUT2B_n 20 41 OUT7B_p 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p n p n p n p n p n p n p n p n p n p n _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ A A B B A A B B K K K K B B A A B B A A 3 3 3 3 4 4 4 4 L L L L 5 5 5 5 6 6 6 6 T T T T T T T T C C C C T T T T T T T T U U U U U U U U A A L L U U U U U U U U O O O O O O O O O O O O O O O O PINFUNCTIONS NUMBER PIN DESCRIPTION OFPINS NAME NUMBER 5 AVDD 9,52,66,71,74 Analogpowersupply,1.8V 6 AGND 3,6,55,58,61,80 Analogground 2 LVDD 11,49 DigitalandI/Opowersupply,1.8V 2 LGND 12,50 Digitalground 1 CLKN 73 Negativedifferentialclock–TieCLKNtoGNDforsingle-endedclock 1 CLKP 72 Positivedifferentialclock 2 LCLKP,LCLKN 31,32 DifferentialLVDSbitclock(7X) 2 ACLKP,ACLKN 29,30 DifferentialLVDSframeclock(1X) 2 IN1P,IN1N 78,79 Differentialinputsignal,Channel1 2 IN2P,IN2N 1,2 Differentialinputsignal,Channel2 2 IN3P,IN3N 4,5 Differentialinputsignal,Channel3 2 IN4P,IN4N 7,8 Differentialinputsignal,Channel4 2 IN5P,IN5N 53,54 Differentialinputsignal,Channel5 2 IN6P,IN6N 56,57 Differentialinputsignal,Channel6 2 IN7P,IN7N 59,60 Differentialinputsignal,Channel7 2 IN8P,IN8N 62,63 Differentialinputsignal,Channel8 2 OUT1A_P,OUT1A_N 13,14 DifferentialLVDSdataoutput,wire1,channel1 Copyright©2011–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS5292 ADS5292 SLAS788B–NOVEMBER2011–REVISEDJULY2012 www.ti.com PINFUNCTIONS(continued) NUMBER PIN DESCRIPTION OFPINS NAME NUMBER 2 OUT1B_P,OUT1B_N 15,16 DifferentialLVDSdataoutput,wire2,channel1 2 OUT2A_P,OUT2A_N 17,18 DifferentialLVDSdataoutput,wire1,channel2 2 OUT2B_P,OUT2B_N 19,20 DifferentialLVDSdataoutput,wire2,channel2 2 OUT3A_P,OUT3A_N 21,22 DifferentialLVDSdataoutput,wire1,channel3 2 OUT3B_P,OUT3B_N 23,24 DifferentialLVDSdataoutput,wire2,channel3 2 OUT4A_P,OUT4A_N 25,26 DifferentialLVDSdataoutput,wire1,channel4 2 OUT4B_P,OUT4B_N 27,28 DifferentialLVDSdataoutput,wire2,channel4 2 OUT5A_P,OUT5A_N 35,36 DifferentialLVDSdataoutput,wire1,channel5 2 OUT5B_P,OUT5B_N 33,34 DifferentialLVDSdataoutput,wire2,channel5 2 OUT6A_P,OUT6A_N 39,40 DifferentialLVDSdataoutput,wire1,channel6 2 OUT6B_P,OUT6B_N 37,38 DifferentialLVDSdataoutput,wire2,channel6 2 OUT7A_P,OUT7A_N 43,44 DifferentialLVDSdataoutput,wire1,channel7 2 OUT7B_P,OUT7B_N 41,42 DifferentialLVDSdataoutput,wire2,channel7 2 OUT8A_P,OUT8A_N 47,48 DifferentialLVDSdataoutput,wire1,channel8 2 OUT8B_P,OUT8B_N 45,46 DifferentialLVDSdataoutput,wire2,channel8 1 PD 10 Powerdowncontrolinput.ActiveHigh.Thepinhasaninternal220-kΩpulldownresistor. 1 REFB 69 Negativereferenceinput/output 1 REFT 70 Positivereferenceinput/output 1 VCM 68 Common-modeoutputpin,0.95Voutput.Thispincanbeconfiguredastheexternalreference voltage(1.5V)inputpinaswell.SeeReg0x42. 1 RESET 51 ActiveHIGHRESETinput.Thepinhasaninternal220-kΩpulldownresistor. 1 SCLK 77 Serialclockinput.Thepinhasaninternal220-kΩpulldownresistor. 1 SDATA 76 Serialdatainput.Thepinhasaninternal220-kΩpulldownresistor. 1 SDOUT 64 Serialdatareadout.Thispinisinthehigh-impedancestateafterreset.Whenthe<READOUT>bit isset,theSDOUTpinbecomesactive.ThisisaCMOSdigitaloutputrunningfromtheAVDD supply. 1 CSZ 75 Serialenablechipselect–activelowdigitalinput 1 SYNC 65 Inputsignaltosynchronizechannelsandchipswhenusedwithreducedoutputdatarates.Ifitis notused,adda≤10KΩpull-downresistor. 1 NC 67 NoConnection.Mustleavefloated 4 SubmitDocumentationFeedback Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):ADS5292 ADS5292 www.ti.com SLAS788B–NOVEMBER2011–REVISEDJULY2012 ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX Supplyvoltage AVDD –0.3 2.2 V LVDD –0.3 2.2 V Voltage betweenAGNDandLGND –0.3 0.3 V atanaloginputs –0.3 min[2.2,AVDD+0.3] V atdigitalinputs,CLKN,CLKP(2),RESET,SCLK,SDATA,CSZ –0.3 min[2.2,AVDD+0.3] V atdigitaloutputs –0.3 min[2.2,LVDD+0.3] V Maximumjunctiontemperature(T),anycondition 105 °C J Storagetemperaturerange –55 150 °C Operatingtemperaturerange -40 85 °C HumanBodyModel(HBM) 2000 V ESDRatings ChargedDeviceModel(CDM) 500 V (1) Stressesabovethoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating conditions”isnotimpliedExposuretoabsolutemaximumratedconditionsforextendedperiodsmaydegradedevicereliability. (2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKNis<|0.3V|.This preventstheESDprotectiondiodesattheclockinputpinsfromturningon. THERMAL INFORMATION ADS5292 THERMALMETRIC(1) UNITS PFP(80PINS) θ Junction-to-ambientthermalresistance 30.8 JA θ Junction-to-case(top)thermalresistance 6.3 JCtop θ Junction-to-boardthermalresistance 8.3 JB °C/W ψ Junction-to-topcharacterizationparameter 0.2 JT ψ Junction-to-boardcharacterizationparameter 8.2 JB θ Junction-to-case(bottom)thermalresistance 0.3 JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. Copyright©2011–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS5292 ADS5292 SLAS788B–NOVEMBER2011–REVISEDJULY2012 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT SUPPLIES AVDD Analogsupplyvoltage 1.7 1.8 1.9 V LVDD Digitalsupplyvoltage 1.7 1.8 1.9 V ANALOGINPUTS/OUTPUTS Differentialinputvoltagerange 2 V PP Inputcommon-modevoltage 0.95±0.05 V REF Externalreferencemode 1.45 V T REF Externalreferencemode 0.45 V B VCM ExternalReferencemodeInput 1.5 V Common-modevoltageoutput 0.95 V MaximumInputFrequency (1) 2V amplitude 80 MHz PP CLOCKINPUTS ADCClockinputsamplerate 10 80 MSPS Sinewave,AC-coupled 0.2 1.5 InputClockamplitudedifferential(V - (CLKP) LVPECL,AC-coupled 0.2 1.6 V V )peak-to-peak PP (CLKN) LVDS,AC-coupled 0.2 0.7 V <0.3 V IL InputClockCMOSsingle-ended(V ) (CLKP) V >1.5 V IH Inputclockdutycycle 35% 50% 65% DIGITALOUTPUTS 1x(sample MSPS ACLKPandACLKNoutputs(LVDS),1-wireinterface rate) 6x(sample MSPS LCLKPandLCLKNoutputs(LVDS),1-wireinterface rate) 0.5x(sample MSPS ACLKPandACLKNoutputs(LVDS),2-wireinterface rate) 3x(sample MSPS LCLKPandLCLKNoutputs(LVDS),2-wireinterface rate) Maximumdatarate,2-wireinterface 480 MSPS Maximumdatarate,1-wireinterface 960 MSPS C MaximumexternalcapacitancefromeachoutputpintoLGND 5 pF LOAD R DifferentialloadresistancebetweentheLVDSoutputpairs 100 Ω LOAD T Operatingfree-airtemperature -40 85 °C A (1) SeetheLargeandSmallSignalInputBandwidthsection. 6 SubmitDocumentationFeedback Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):ADS5292 ADS5292 www.ti.com SLAS788B–NOVEMBER2011–REVISEDJULY2012 ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE Typicalvaluesareat25°C,AVDD=1.8V,LVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,12Bit/80 MSPS,ADCisconfiguredininternalreferencemode(unlessotherwisenoted).MINandMAXvaluesareacrossthefull temperaturerangeT =–40°CtoT =85°C,AVDD=1.8V,LVDD=1.8V. MIN MAX PARAMETERS CONDITIONS MIN TYP MAX UNITS ACPERFORMANCE fin=5MHz,80MSPS.14bitsmode 72 fin=5MHz,80MSPS 67.5 70 SNR Signal-to-noiseratio dBFS fin=30MHz,80MSPS 69.8 fin=5MHz,80MSPS,Decimationfilter=2 71.5 Signal-to-noiseanddistortion fin=5MHz,80MSPS 69.8 SINAD dBFS ratio fin=30MHz,80MSPS 69.3 ENOB Effectivenumberofbits fin=5MHz 11.3 LSB DNL Differentialnonlinearity fin=5MHz –0.8 ±0.05 0.8 LSB INL Integralnonlinearity fin=5MHz 0.4 1 LSB fin=5MHz 72.5 85 SFDR Spurious-freedynamicrange dBc fin=30MHz 80 fin=5MHz 71 81.5 THD Totalharmonicdistortion dBc fin=30MHz 78 fin=5MHz 72.5 88 HD2 Second-harmonicdistortion dBc fin=30MHz 80 fin=5MHz 72.5 85 HD3 Third-harmonicdistortion dBc fin=30MHz 78.5 fin=5MHz 91 WorstspurexcludingHD2,HD3 fin=30MHz 83 dBc fin=65MHz 76 IMD3 Intermodualtiondistortion fin=5MHzat–7dBFS,f2=10MHzat–7dBFS 82 dBc Recoverytowithin1%offullscalevaluefor6-dBoverloadwithsinewave Clock Overloadrecovery 1 input Cycle fin=10MHz;VOUT=–1dBFSsignalappliedon farchannel 90 XTALK Cross-talk aggressorchannelnosignalappliedonvictim dB channel nearchannel 85 Phasenoise 5MHz,1kHzoffcarrier –138 dBc/Hz ANALOGINPUT/OUTPUT Differentialinputvoltagerange 2 Vpp (0-dBgain) Rin DifferentialInputResistance AtDC 2 kΩ Cin DifferentialInputCapacitance AtDC 2.2 pF Analoginputbandwidth Witha50Ωsourceimpedance 550 MHz Analoginputcommon-mode µA/MSP 1.6 current(perinputpin) S VCMcommon-modeoutput 0.95 V voltage VCMoutputcurrentcapability 5 mA DCACCURACY Offseterror Acrossdevicesandacrosschannelswithinadevice –20 20 mV Temperaturecoefficientofoffset <0.01 mV/°C error Gainerrorduetointernal EGREF referenceinaccuracyalone –2 2 %FS EGCHAN Gainerrorofchannelalone 0.5 %FS Temperaturecoefficentof <0.01 %FS/°C EGCHAN Copyright©2011–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS5292 ADS5292 SLAS788B–NOVEMBER2011–REVISEDJULY2012 www.ti.com ELECTRICAL CHARACTERISTICS DYNAMIC PERFORMANCE (continued) Typicalvaluesareat25°C,AVDD=1.8V,LVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,12Bit/80 MSPS,ADCisconfiguredininternalreferencemode(unlessotherwisenoted).MINandMAXvaluesareacrossthefull temperaturerangeT =–40°CtoT =85°C,AVDD=1.8V,LVDD=1.8V. MIN MAX PARAMETERS CONDITIONS MIN TYP MAX UNITS POWERSUPPLY 80MSPS/12-Bit,2-wireLVDS 66 50MSPS/12Bit,1-wireLVDS 48 Powerconsumption mW/CH 40MSPS/12Bit,1-wireLVDS 43 80MSPS/12Bit,1-wiredecimationfilter=2,1-wireLVDS 87 80MSPS,12Bit 182 206 AVDD 65MSPS,12Bit 162 mA 40MSPS,12Bit 130 80MSPS/12-Bit,2-wireLVDS 112 125 50MSPS/12Bit,1-wireLVDS 67 LVDD 40MSPS/12Bit,1-wireLVDS 61 mA 80MSPS/12Bit,Decimationfilter=2, 198 1-wireLVDS Partialpowerdown,80MHz,2-wireLVDS 175 Power-downpowerconsumption mW Completepowerdown 50 Powersupplymodulationratio Carrier=5MHz,fN=10kHzat50mVPPsignalonAVDD 30 dBc Powersupplyrejectionratio ACpowersupplyrejectionratiof=10kHz 55 dBc 8 SubmitDocumentationFeedback Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):ADS5292 ADS5292 www.ti.com SLAS788B–NOVEMBER2011–REVISEDJULY2012 DIGITAL CHARACTERISTICS TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic level0or1.AVDD=1.8V,LVDD=1.8V PARAMETERS CONDITION MIN TYP MAX UNITS DIGITALINPUTS/OUTPUTS Alldigitalinputssupport1.8-Vand3.3-VCMOSlogic V Logichighinputvoltage 1.3 V IH levels. V Logiclowinputvoltage 0.4 V IL I Logichighinputcurrent V =1.8V 6 µA IH HIGH I Logiclowinputcurrent V =0V <0.1 µA IL LOW V Logichighoutputvoltage AVDD-0.1 V OH V Logiclowoutputvoltage 0.2 V OL LVDSOUTPUTS V High-leveloutputdifferentialvoltage 100Ωexternaltermination 240 350 405 mV ODH V Low-leveloutputdifferentialvoltage 100Ωexternaltermination –240 –350 –405 mV ODL V Outputcommon-modevoltage 900 1100 1300 mV OCM OUTP LogLico g0ic0 Logic 0 V = -350 mV* V = +350 mV* ODL ODH OUTM V OCM GGNNDD *With external 100-Wtermination Figure2. LVDSOutputVoltageLevels Copyright©2011–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS5292 ADS5292 SLAS788B–NOVEMBER2011–REVISEDJULY2012 www.ti.com TIMING REQUIREMENTS(1)(2)(3) Typicalvaluesareat25°C,AVDD=1.8V,LVDD=1.8V,samplingfrequency=80MSPS,12-bit,sine-waveinputclock= 1.5-Vppclockamplitude,C =5pF,R =100Ω,unlessotherwisenoted.MINandMAXvaluesareacrossthefull LOAD LOAD temperaturerangeT =–40°CtoT =85°C,AVDD=1.8V,LVDD=1.7Vto1.9V. MIN MAX PARAMETERS CONDITIONS MIN TYP MAX UNITS Thedelayintimebetweentherisingedgeoftheinput ta Aperturedelay samplingclockandtheactualtimeatwhichthesampling 4 ns occurs Aperturedelayvariation Acrosschannelswithinthesamedevice ±175 ps AcrossdevicesatsametemperatureandLVDDsupply 2.5 ns voltage tj AperturejitterRMS 320 fsrms td Datalatency 1-wireLVDSoutputinterface 11 Clockcycles 2-wireLVDSoutputinterface 15 Clockcycles tSU Datasetuptime 80MSPS,2wireLVDS,6xserialization 0.25 0.63 ns tH Dataholdtime 80MSPS,2wireLVDS,6xserialization 0.65 1 ns Inputclockrisingedge(zerocross)toframeclockrising SeeTable1and Clockpropagationdelay ns tPROG edge(zerocross) Table2 VariationoftPROG Betweentwodevicesunderthesameconditions ±0.75 ns LVDSbitclockdutycycle 50% Bitclockcycle-to-cyclejitter 40 psrms Frameclockcycle-to-cycle 70 psrms jitter tRISE Datarisetime Risetimeisfrom-100mVto+100mV 0.2 ns tFALL Datafalltime Falltimeisfrom+100mVto-100mV 0.2 ns tCLKRISE Outputclockrisetime Risetimeisfrom-100mVto+100mV 0.18 ns tCLKFALL Outputclockfalltime Falltimeisfrom+100mVto-100mV 0.16 ns TimetovaliddataaftercomingoutofCOMPLETE tWAKE Wake-upTime POWER-DOWNmode 100 µs TimetovaliddataaftercomingoutofPARTIALPOWER- DOWNmode(withclockcontinuingtorunduringpower- 5 µs down) (1) Timingparametersareensuredbydesignandcharacterizationandnottestedinproduction. (2) Measurementsaredonewithatransmissionlineof100-Ωcharacteristicimpedancebetweenthedeviceandtheload.Setupandhold timespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock. (3) DatavalidreferstologicHIGHof100mVandlogicLOWof–100mV. 10 SubmitDocumentationFeedback Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):ADS5292
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