NASA Technical Reports Server (NTRS) 19940017221: The 1992 4th NASA SERC Symposium on VLSI Design

422 Pages·22.8 MB·English

by  NASA Technical Reports Server (NTRS)

4th NASA Symposium
on VLSI Design
University of Idaho
Moscow, Idaho
October 29-30, 1992
(NASA-CR-194591) THE 1992 4TH NASA N94-21694
•5.
SERC SYMPOSIUM ON VLSI DESIGN —THRU—
(Idaho Univ.) 422 p N94-21735
Unclas
G3/33 0191442
Cover design bv Peter Vincent
4th NASA Symposium on VLSI Design i
Welcome to the fourth annual NASA Symposium on VLSI Design, co-sponsored by the
IEEE. Each year this symposium is organized by the NASA Space Engineering Research
Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting
of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is
to develop new electronic technologies that will meet next generation electronic data system
needs. The symposium provides insights into developments in VLSI and digital systems
which can be used to increase data systems performance.
The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations
by an outstanding set of individuals from national laboratories, the electronics industry and
universities. These speakers share insights into next generation advances that will serve as
a basis for future VLSI design.
In spite of the present economic conditions, interest in the conference has remained steady
with 42 papers in 10 categories included in this years proceedings. National Laboratories are
represented by Rockwell International Science Center, NCCOSC Research and Development,
Jet Propulsion Laboratory and the Johns Hopkins University Applied Physics Laboratory.
Private industry is represented by Texas Instruments, Advanced Hardware Architectures and
Spacebourne Inc. Universities are represented by Cornell University, Utah State University,
University of Alabama, Washington State University, University of Calgary, University of
Southwestern Louisiana , Nanyang Technological University, Syracuse University, Concordia
University, University of California at Davis and Irving, California State University at Fuller-
ton Colorado State University, University of Toledo, University of Peradeniya, University of
New Mexico and the University of Idaho. In addition we are happy to welcome a number of
papers presented by international authors.
There are individuals whose assistance was critical to the success of this symposium.
Barbara Martin worked long hours to assemble the conference proceedings. The efforts of
these professionals were vital and are greatly appreciated. I hope you enjoy your stay in
Coeur d'Alene, Idaho.
Sterling R. Whitaker
11
Session 1 — Featured Presentations I
Chairman: Gary Maki
Applications of Correlator Chips in Radio Science 1.1
Jon Hagen
Single Event Phenomena: Testing and Prediction 1.2
James D. Kinnison
Heterojunction Bipolar Transistor Technology for Data Acquisition and 1.3
Communication
K.C. Wang and D.T. Cheung
Session 2 — VLSI Architectures
Chairman: Kelly Cameron
A New Eddy Current Model for Magnetic Bearing Control System Design?. 1
Joseph J. Feeley and Daniel Ahlstrom
Design of a New Squaring Function for the Viterbi Algorithm 2.2
Aral Eshraghi, Terri Fiez, Kel Winters and Thomas Fischer
A 20MHz CMOS Reorder Buffer for a Superscalar Microprocessor 2.3
John Lenell, Steve Wallace and Nader Bagherzadeh
Analog/Digital pH Meter System I.C. 2.4
Paul Vincent and Jea Park
An 18 Bit 50 kHz ADC for Low Earth Orbit 2.5
Donald C. Thelen
4th NASA Symposium on VLSI Design iii
Session 3 — Design Synthesis
Chairman: James Frenzel
On the Decomposition of Synchronous State Machines Using Sequence 3.1
Invariant State Machines
K. Hebbalalu, S. Whitaker and K. Cameron
A Heuristic-Based Scheduling Algorithm for High Level Synthesis 3.2
Gulam Mohamed, Tan Han Ngee and Chng Chew Lye
Evaluation of Floating Point Sum or Difference of Products in Carry 3.3
Save Domain
Abdul Wahab, S.S. Erdogan and A.B. Premkumar
A Statistical-based Scheduling Algorithm in Automated Data Path 3.4
Synthesis
Byung Wook Jeon and Chidchanok Lursinsap
Micro-rollback and Self-recovery Synthesis 3.5
Byung Wook Jeon and Chidchanok Lursinsap
Session 4 — Featured Presentations II
Chairman: Sterling Whitaker
System Development Using VLSI for Space Applications 4.1
T.R. McKnight, D.E. Rodriguez, J.C. Barnett, and C.R. Valverde
NASA SERC Digital Correlator Projects 4.2
John Canaris
Fully Depleted Silicon-on-Sapphire and Its Application to Advanced 4.3
VLSI Design
Bruce Offord
IV
Session 5 — VLSI Design
Chairman: Kel Winters
Design and Test of Field Programmable Gate Arrays in Space Appli- 5.1
cations
Priscilla L. McKerracher, Russel P. Cain, Jon C. Barnett, William S. Green and
James D. Kinnison
Defect-Sensitivity Analysis of an SEU Immune CMOS Logic Family 5.2
Eric H. Ingermann and James F. Frenzel
Dimension Scaling Effects on the Yield Sensitivity of HEMT Digital 5.3
Circuits
Jogendra Sarker and John Purviance
Links between N-Modular Redundancy and the Theory of Error- 5.4
Correcting Codes
V. Bobin, S. Whitaker, and G. Maki
Reduction of Blocking Effects for the JPEG Baseline Image Compres- 5.5
sion Standard
Gregary C. Zweigle and Roberto Bamberger
Session 6 — Verification
Chairman: Phil Windley
A Novel Visual Hardware Behavioral Language 6.1
Xueqin Li and H.D. Cheng
A Mechanized Process Algebra for Verification of Device Synchroniza- 6.2
tion Process
E. Thomas Schubert
HDL to Verification Logic Translator 6.3
Jody W. Gambles and Phillip J. Windley
A Simple Modern Correctness Condition for a Space-Based High- 6.4
Performance Microprocessor
David K. Probst and Hon F. Li
Instruction Set Commutativity 6.5
Phillip J. Windley
4th NASA Symposium on VLSI Design
Session 7 — Tools and Methods
Chairman: Jonathan Gibson
A Mean Field Neural Network for Hierarchical Module Placement 7.1
M. Kemal Unaltuna and Vijay Pitchumani
Detection of Feed-Through Faults in CMOS Storage Elements 7.2
Waleed K Al-Assadi. Y. Malaiya and A. Jayasumana
Schematic Driven Layout of Reed Solomon Encoders 7.3
Kari Arave, John Canaris, Lowell Miles and Sterling Whitaker
Interpolative Modeling of GaAs FET S-parameter Data Bases for Use 7.4
in Monte Carlo Simulation
Lowell Campbell and John Purviance
Teaching VLSI in High School 7.5
Larry Volkening
Session 8 — VLSI Design
Chairman: Jody Gambles
Bit-Systolic Arithmetic Arrays Using Dynamic Differential Gallium Ar- 8.1
senide Circuits
Grant Beagles, Kel Winters and A.G. Eldin
A VLSI Implementation of DCT Using Pass Transistor Technology 8.2
S. Kamath, Doug Lynn and Sterling Whitaker
A High Speed CMOS A/D Converter 8.3
Don R. Wiseman and Sterling Whitaker
Behavior of Faulty Double BJT BiCMOS Logic Gates 8.4
Sankaran M. Menon, Yashwant K. Malaiya and Anura P. Jayasumana
On Fast Carry Select Adders 8.5
Manju Shamanna and Sterling Whitaker
VI
Session 9 — Cache Architectures
Chairman: Joseph Feeley
A DRAM Compiler Algorithm for High Performance VLSI Embedded 9.1
Memories
A.G. Eldin
A Novel Cache Mechanism 9.2
J.A. Gunawardena
A Set-Associative, Fault-Tolerant Cache Design 9.3
Dan Lamet and James F. Frenzel
Session 10 - Correlators
Chairman: John Canaris
A 1 GHZ Sample Rate, 256-Channel, 1-Bit Quantization , CMOS, Dig- 10.1
ital Correlator Chip
C, Timoc, T. Tran and J. Wongso
Low Power, CMOS Digital Auto correlator Spectrometer for Space- 10.2
bourne Applications
Kumar Chandra and William J. Wilson
A Real Time Correlator Using Distributed Arithmetic Principles 10.3
A. Benjamin Premkumar and T. Srikanthan
Low Energy CMOS for Space Applications 10.4
Ramesh Panwar and Leon Alkalaj
4th NASA Symposium on VLSI Design vn
List of Authors
Ahlstrom, D 2.1 Li, H 6.4
Al-Assadi, W 7.2 Li, Xueqin 6.1
Alkalaj,L. 10.4 Lursinsap, C 3.4
Arave, K 7.3 3.5
Bagherzadeh, N 2.3 Lye, C 3.2
Bamberger, R 5.5 Lynn, D 8.2
Barnett, J 4.1 Malaiya, Y 7.2
5.1 8.4
Beagles, G 8.1 Maki, G 5.4
Bobin, V 5.4 McKerracher, P 5.1
Cain, R 5.1 McKnight, T 4.1
Cameron, K 3.1 Menon, S 8.4
Campbell, L 7.4 Miles, L 7.3
Canaris, J 4.2 Mohamed, G 3.2
7.3 Ngee, T 3.2
Chandra, K 10.2 Offord, B 4.3
Cheng, H 6.1 Panwar, R 10.4
Cheung, D 1.3 Park, J 2.4
Eldin, A 8.1 Pitchumani, V 7.1
9.1 Premkumar, A 3.3
Erdogan, S 3.3 10.3
Eshraghi, A 2.2 Probst, D 6.4
Feeley, J 2.1 Purviance, J 5.3
Fiez, T 2.2 7.4
Fischer, T 2.2 Rodriguez, D 4.1
Frenzel, J 5.2 Sarker, J 5.3
9.3 Schubert, E 6.2
Gambles, J 6.3 Shamanna, M 8.5
Green, W 5.1 Srikanthan, T 10.3
Gunawardena, J 9.2 Tran, T 10.1
Hagen, J 1.1 Thelen, D 2.5
Hebbalalu, K 3.1 Timoc, C 10.1
Ingermann, E 5.2 Unaltuna, M 7.1
Jayasumana, J 7.2 Valverde, C 4.1
8.4 Volkening, L 7.5
Jeon, B 3.4 Vincent, P 2.4
3.5 Wahab, A 3.3
Kamath, S 8.2 Wang, K 1.3
Kinnison, J 1.2 Wallace, S 2.3
5.1 Whitaker, S 3.1
Lamet, D 9.3 5.4
Lenell, J 2.3 7.3
Vlll
8.2
Whitaker, S 8.3
8.5
Wilson, W 10.2
Windley, P 6.3
6.5
Winters, K 2.2
8.1
Wiseman, D 8.3
Wongso, J 10.1
Zweigle, G 5.5