Nano-CMOS Circuit and Physical Design

408 Pages·2004·5.647 MB·English

by  Ban Wong, Anurag Mittal, Yu Cao, Greg W. Starr

NANO-CMOS CIRCUIT
AND PHYSICAL DESIGN
NANO-CMOS CIRCUIT
AND PHYSICAL DESIGN
Ban P. Wong
NVIDIA
Anurag Mittal
VirageLogic,Inc.
Yu Cao
UniversityofCalifornia–Berkeley
Greg Starr
Xilinx
A JOHN WILEY & SONS, INC., PUBLICATION
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LibraryofCongressCataloging-in-PublicationData:
Nano-CMOScircuitandphysicaldesign/BanP.Wong...[etal.].
p.cm.
Includesbibliographicalreferencesandindex.
ISBN0-471-46610-7(cloth)
1.Metaloxidesemiconductors,Complementary–Designandconstruction.2.
Integratedcircuits–Designandconstruction.I.Wong,BanP.,1953–
TK7871.99.M44N362004
621.39(cid:1)732–dc22
2004002212
PrintedintheUnitedStatesofAmerica.
10987654321
CONTENTS
FOREWORD xiii
PREFACE xv
1 NANO-CMOSSCALINGPROBLEMSANDIMPLICATIONS 1
1.1 Design Methodology in the Nano-CMOS Era 1
1.2 Innovations Needed to Continue Performance
Scaling 3
1.3 Overview of Sub-100-nm Scaling Challenges
and Subwavelength Optical Lithography 6
1.3.1 Back-End-of-Line Challenges (Metallization) 6
1.3.2 Front-End-of-Line Challenges (Transistors) 12
1.4 Process Control and Reliability 15
1.5 Lithographic Issues and Mask Data Explosion 16
1.6 New Breed of Circuit and Physical Design
Engineers 17
1.7 Modeling Challenges 17
1.8 Need for Design Methodology Changes 19
1.9 Summary 21
References 21
v
vi CONTENTS
PARTI PROCESSTECHNOLOGYANDSUBWAVELENGTH
OPTICALLITHOGRAPHY:PHYSICS,THEORYOFOPERATION,
ISSUES,ANDSOLUTIONS
2 CMOSDEVICEANDPROCESSTECHNOLOGY 24
2.1 Equipment Requirements for Front-End Processing 24
2.1.1 Technical Background 24
2.1.2 Gate Dielectric Scaling 26
2.1.3 Strain Engineering 33
2.1.4 Rapid Thermal Processing Technology 34
2.2 Front-End-Device Problems in CMOS Scaling 41
2.2.1 CMOS Scaling Challenges 41
2.2.2 Quantum Effects Model 43
2.2.3 Polysilicon Gate Depletion Effects 45
2.2.4 Metal Gate Electrodes 48
2.2.5 Direct-Tunneling Gate Leakage 49
2.2.6 Parasitic Capacitance 52
2.2.7 Reliability Concerns 56
2.3 Back-End-of-Line Technology 58
2.3.1 Interconnect Scaling 59
2.3.2 Copper Wire Technology 61
2.3.3 Low-κ Dielectric Challenges 64
2.3.4 Future Global Interconnect Technology 65
References 66
3 THEORYANDPRACTICALITIESOF
SUBWAVELENGTHOPTICALLITHOGRAPHY 73
3.1 Introduction and Simple Imaging Theory 73
3.2 Challenges for the 100-nm Node 76
3.2.1 κ-Factor for the 100-nm Node 77
3.2.2 Significant Process Variations 78
3.2.3 Impact of Low-κ Imaging on Process
Sensitivities 82
3.2.4 Low-κ Imaging and Impact on Depth
of Focus 83
3.2.5 Low-κ Imaging and Exposure Tolerance 84
3.2.6 Low-κ Imaging and Impact on Mask Error
Enhancement Factor 84
3.2.7 Low-κ Imaging and Sensitivity to Aberrations 86
CONTENTS vii
3.2.8 Low-κ Imaging and CD Variation as a Function
of Pitch 86
3.2.9 Low-κ Imaging and Corner Rounding Radius 89
3.3 Resolution Enhancement Techniques: Physics 91
3.3.1 Specialized Illumination Patterns 92
3.3.2 Optical Proximity Corrections 94
3.3.3 Subresolution Assist Features 101
3.3.4 Alternating Phase-Shift Masks 103
3.4 Physical Design Style Impact on RET and OPC Complexity 107
3.4.1 Specialized Illumination Conditions 108
3.4.2 Two-Dimensional Layouts 111
3.4.3 Alternating Phase-Shift Masks 114
3.4.4 Mask Costs 118
3.5 The Road Ahead: Future Lithographic Technologies 121
3.5.1 The Evolutionary Path: 157-nm Lithography 121
3.5.2 Still Evolutionary: Immersion Lithography 122
3.5.3 Quantum Leap: EUV Lithography 124
3.5.4 Particle Beam Lithography 126
3.5.5 Direct-Write Electron Beam Tools 126
References 130
PARTII PROCESSSCALINGIMPACTONDESIGN
4 MIXED-SIGNALCIRCUITDESIGN 134
4.1 Introduction 134
4.2 Design Considerations 134
4.3 Device Modeling 135
4.4 Passive Components 142
4.5 Design Methodology 146
4.5.1 Benchmark Circuits 146
4.5.2 Design Using Thin Oxide Devices 146
4.5.3 Design Using Thick Oxide Devices 148
4.6 Low-Voltage Techniques 150
4.6.1 Current Mirrors 150
4.6.2 Input Stages 152
4.6.3 Output Stages 153
4.6.4 Bandgap References 154
4.7 Design Procedures 155
4.8 Electrostatic Discharge Protection 157
viii CONTENTS
4.8.1 Multiple-Supply Concerns 157
4.9 Noise Isolation 159
4.9.1 Guard Ring Structures 159
4.9.2 Isolated NMOS Devices 161
4.9.3 Epitaxial Material versus Bulk Silicon 161
4.10 Decoupling 162
4.11 Power Busing 166
4.12 Integration Problems 167
4.12.1 Corner Regions 167
4.12.2 Neighboring Circuitry 167
4.13 Summary 168
References 168
5 ELECTROSTATICDISCHARGEPROTECTIONDESIGN 172
5.1 Introduction 172
5.2 ESD Standards and Models 173
5.3 ESD Protection Design 173
5.3.1 ESD Protection Scheme 173
5.3.2 Turn-on Uniformity of ESD Protection
Devices 175
5.3.3 ESD Implantation and Silicide Blocking 177
5.3.4 ESD Protection Guidelines 178
5.4 Low-C ESD Protection Design for High-Speed I/O 178
5.4.1 ESD Protection for High-Speed I/O or Analog Pins 178
5.4.2 Low-C ESD Protection Design 180
5.4.3 Input Capacitance Calculations 183
5.4.4 ESD Robustness 185
5.4.5 Turn-on Verification 186
5.5 ESD Protection Design for Mixed-Voltage I/O 190
5.5.1 Mixed-Voltage I/O Interfaces 190
5.5.2 ESD Concerns for Mixed-Voltage I/O Interfaces 191
5.5.3 ESD Protection Device for a Mixed-Voltage I/O
Interface 192
5.5.4 ESD Protection Circuit Design for a Mixed-Voltage
I/O Interface 195
5.5.5 ESD Robustness 198
5.5.6 Turn-on Verification 199
5.6 SCR Devices for ESD Protection 200
5.6.1 Turn-on Mechanism of SCR Devices 201
CONTENTS ix
5.6.2 SCR-Based Devices for CMOS On-Chip ESD
Protection 202
5.6.3 SCR Latch-up Engineering 210
5.7 Summary 212
References 213
6 INPUT/OUTPUTDESIGN 220
6.1 Introduction 220
6.2 I/O Standards 221
6.3 Signal Transfer 222
6.3.1 Single-Ended Buffers 223
6.3.2 Differential Buffers 223
6.4 ESD Protection 227
6.5 I/O Switching Noise 228
6.6 Termination 232
6.7 Impedance Matching 234
6.8 Preemphasis 235
6.9 Equalization 237
6.10 Conclusion 238
References 239
7 DRAM 241
7.1 Introduction 241
7.2 DRAM Basics 241
7.3 Scaling the Capacitor 245
7.4 Scaling the Array Transistor 247
7.5 Scaling the Sense Amplifier 249
7.6 Summary 253
References 253
8 SIGNALINTEGRITYPROBLEMSINON-CHIP
INTERCONNECTS 255
8.1 Introduction 255
8.1.1 Interconnect Figures of Merit 258
8.2 Interconnect Parasitics Extraction 259
8.2.1 Circuit Representation of Interconnects 260
8.2.2 RC Extraction 263
8.2.3 Inductance Extraction 267
x CONTENTS
8.3 Signal Integrity Analysis 271
8.3.1 Interconnect Driver Models 272
8.3.2 RC Interconnect Analysis 274
8.3.3 RLC Interconnect Analysis 277
8.3.4 Noise-Aware Timing Analysis 281
8.4 Design Solutions for Signal Integrity 283
8.4.1 Physical Design Techniques 284
8.4.2 Circuit Techniques 288
8.5 Summary 293
References 294
9 ULTRALOWPOWERCIRCUITDESIGN 298
9.1 Introduction 298
9.2 Design-Time Low-Power Techniques 300
9.2.1 System- and Architecture-Level Design-Time
Techniques 300
9.2.2 Circuit-Level Design-Time Techniques 300
9.2.3 Memory Techniques at Design Time 305
9.3 Run-Time Low-Power Techniques 311
9.3.1 System- and Architecture-Level Run-Time
Techniques 311
9.3.2 Circuit-Level Run-Time Techniques 313
9.3.3 Memory Techniques at Run Time 316
9.4 Technology Innovations for Low-Power Design 320
9.4.1 Novel Device Technologies 320
9.4.2 Assembly Technology Innovations 321
9.5 Perspectives for Future Ultralow-Power Design 321
9.5.1 Subthreshold Circuit Operation 322
9.5.2 Fault-Tolerant Design 322
9.5.3 Asynchronous versus Synchronous Design 323
9.5.4 Gate-Induced Leakage Suppression Schemes 323
References 324
PARTIII IMPACTOFPHYSICALDESIGNON
MANUFACTURING/YIELDANDPERFORMANCE
10 DESIGNFORMANUFACTURABILITY 331
10.1 Introduction 331
10.2 Comparison of Optimal and Suboptimal Layouts 332
CONTENTS xi
10.3 Global Route DFM 338
10.4 Analog DFM 339
10.5 Some Rules of Thumb 341
10.6 Summary 342
References 342
11 DESIGNFORVARIABILITY 343
11.1 Impact of Variations on Future Design 343
11.1.1 Parametric Variations in Circuit Design 343
11.1.2 Impact on Circuit Performance 345
11.2 Strategies to Mitigate Impact Due to Variations 347
11.2.1 Clock Distribution Strategies to Minimize Skew 347
11.2.2 SRAM Techniques to Deal with Variations 351
11.2.3 Analog Strategies to Deal with Variations 361
11.2.4 Digital Circuit Strategies to Deal
with Variations 370
11.3 Corner Modeling Methodology for Nano-CMOS
Processes 376
11.3.1 Need for Statistical Models 376
11.3.2 Statistical Model Use 378
11.4 New Features of the BSIM4 Model 381
11.4.1 Halo/Pocket Implant 381
11.4.2 Gate-Induced Drain Leakage and Gate Direct
Tunneling 382
11.4.3 Modeling Challenges 383
11.4.4 Model-Specific Issues 384
11.4.5 Model Summary 385
11.5 Summary 385
References 385
INDEX 389