Nano and giga challenges in microelectronics

264 Pages·2003·25.354 MB·English

by  Jim Greer, Anatoli Korkin, Jan K Labanowski

Nano and Giga Challenges
in Microelectronics
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Nano and Giga Challenges
in Microelectronics
Edited by:
Jim Greer
NMRC, Cork, Ireland
Anatoli Korkin
Motorola, Inc., Phoenix, Arizona, USA
Jan Labanowski
Ohio Supercomputing Centre, Columbus, Ohio, USA
ELSEVIER
2003
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Preface
Microelectronics technologies have reached a presented within the book can help to foster further
new stage in their development: the ultimate research and cross-disciplinary interaction needed
miniaturization of transistors is in sight us gate to surmount the barriers facing future generations
lengths approach atomic dimensions, the intercon- of technology design. This book also serves as a
nect bottleneck is posed to limit circuit speeds, companion to the special issue of the journal Mi-
new material sets are being introduced into mi- croelectronics Engineering, which documents the
croelectronic manufacture at an unprecedented technical papers presented during the Nano and
rate, and alternative technologies to mainstream Giga 2002 meeting.
CMOS are seriously being considered in many It is a great pleasure for the Editors of Nano
cases off financial, not performance, grounds. and Giga Challenges to present these collected
It is against this backdrop of technology change chapters, and we thank each of the authors of this
that the series Nano and Giga Challenges in Micro- volume for sharing their insights and expertise
electronics is being launched. Spawned by a meet- and the sponsors of NGCM2002 for their gracious
ing of the same name held in Moscow in 2002, the support: Digital DNA Lab Motorola, Russian
series is intended to provide tutorial and exposi- Research Center Kurchatov Institute, US Depart-
tory articles on advanced technology problems re- ment of Energy - Nuclear Cities Initiative, Nunn
lated to micro- and nano- technology development. &: Turner Foundation - Nuclear Threat Initiative,
The articles capture the flavor and excitement of Moscow State University, International Science
the Nano and Giga meeting (future meetings are & Technology Center, Elsevier Science, European
planned, with the next to be held in St. Petersburg Office of Aerospace Research and Development
in 2004) with the articles solicited from leading United States Air Force, Russian Federal Nuclear
researchers in representative subject areas. Each Center (VNIIEF), Russian Foundation for Basic
chapter is intended as a self-contained introduction Research, US Office of Naval Research, KINTECH
to an advanced research topic ranging from micro- Kinetic Technologies, and Ohio Supercomputer
electronics materials to molecular electronics, and Center are gratefully acknowledged.
extending through to nanoelectronic circuit archi-
tectures.
The book's intention is to act as an introduction Jim Greer Anatoli Korkin Jan Labanowski
for engineers and researchers wishing to obtain a
NMRC Motorola OSC
fundamental knowledge and a snapshot in time of
the cutting edge in technology research. As a natu- Columbus, Ohio
ral consequence, the Nano and Giga Challenges is
Cork, Ireland Phoenix, Arizona
also a useful reference also for the "gurus" wishing
to keep abreast of the latest directions and chal-
lenges in microelectronic technology development May, 2003
and future trends. The combination of viewpoints
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Contents
Preface v
1. Peter M. Zeitzoff, James A. Hutchby, Gennadi Bersuker, and Howard R.
Huff
Integrated Circuit Technologies: From Conventional CMOS to the
Nanoscale era. 1
2. Konstantin Likharev
Electronics Below 10 nm 27
3. Kevin Lucas, Sergei Postnikov, Cliff Henderson, Scott Hector
Lithography: Concepts, Challenges, and Prospects 69
4. Susanne Stemmer and Darrell G. Schlom
Experimental Investigations of the Stability of Candidate Materials for
High-K Gate Dielectrics in Silicon-Based MOSFETs 129
5.A.L Shluger, Adam Foster
Defects in wide-gap oxides: Computer modelling and challenges 151
6. John Tomfohr, Jun Li, and Otto Sankey
Tunneling Through Single Molecules 223
7. Patrick M. Lenahan
Practical Quantum Computing 237
Subject Index 251
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Nano and Giga Challenges in Microelectronics
Greer at al (Editors)
O 2003 Elsevier Science B. V. All rights reserved
Integrated Circuit Technologies: From Conventional CMOS To The
NanoscaleEra^
Peter M. Zeitzoff ^'\ James A. Hutchby ^, Gennadi Bersuker^, and Howard R. Huff ^.
^International SEMATECH Inc., 2706 Montopolis Drive, Austin, TX 78741.
^Semiconductor Research Corp., P.O. Box 12053, Durham, NC 27709.
Abstract
The development of advanced MOSFETs for future integrated circuit technology generations is discussed from
the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS). Starting from overall
chip circuit requirements, MOSFET and front-end process integration technology requirements and scaling trends
are discussed, as well as some of the key challenges and potential solutions. These include the use of high-k gate
dielectrics, metal gate electrodes, and perhaps the use of non-classical devices such as multiple-gate MOSFETs in
the later stages of the ITRS.
Key words: MOSFET scaling, high-k gate dielectric, non-classical CMOS, FinFET, strained Si on SiGe: enhanced
mobility channel.
1. Introduction per function is halved every one-and-a half to two
years. As a result of following Moore's Law, chip
For over thirty-five years, the integrated circuit speed and functional density have increased expo-
(IC) industry has rapidly and consistently scaled nentially with time while average power dissipation
(reduced) the design rules, increased the chip and per function and cost per function have decreased
wafer size, and improved the design of devices and exponentially with time [5]. In particular, the num-
circuits [1], [2]. In doing so, the industry has been ber of memory bits per chip has quadrupled every
following the well-known Moore's Law [1], [3], [4], three to four years, while the speed of micropro-
which in its simplest form states that the num- cessors has more than doubled every three years,
ber of functions per chip is doubled while the cost based on the increase from about 2 MHz for the
Intel® 8080 in the mid-1970's to well over 1 GHz
* It is an expanded version of a paper, MOSFET and for current leading-edge chips [6], [7]. The design
Front-End Process Integration: Scaling Trends, Chal- rules have been scaled from about 8 /xm in 1972
lenges, and Potential Solutions Through The End Of The to the 130 nm (0.13 fim) dynamic random access
Roadmap^ by Peter M. Zeitzoff, James A. Hutchby, and
memory (DRAM) half pitch of 200rs leading-edge
Howard R. Huff International Journal of High-Speed Elec-
tronics and Systems, vol. 12, pp. 267-293 (2002), Word technologies. (This half pitch is defined as half the
Scientific Publishing Co. Pte Ltd, Singapore. minimum metal or polysilicon pitch for DRAMs,
^ [email protected]