multi-gigabit cmos analog-to-digital converter and mixed-signal demodulator for low-power ...

217 Pages·2011·6.26 MB·English

by  Kevin Chuang

MULTI-GIGABIT CMOS ANALOG-TO-DIGITAL CONVERTER
AND MIXED-SIGNAL DEMODULATOR FOR LOW-POWER
MILLIMETER-WAVE COMMUNICATION SYSTEMS

A Dissertation
Presented to
The Academic Faculty

by

Kevin Shun-Chieh Chuang

In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of Electrical and Computer Engineering

Georgia Institute of Technology
May 2011

Copyright 2011 by Kevin Shun-Chieh Chuang
MULTI-GIGABIT CMOS ANALOG-TO-DIGITAL CONVERTER
AND MIXED-SIGNAL DEMODULATOR FOR LOW-POWER
MILLIMETER-WAVE COMMUNICATION SYSTEMS

Approved by:

Dr. Gee-Kung Chang, Advisor Dr. Geoffrey Ye Li
School of Electrical and Computer School of Electrical and Computer
Engineering Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. Shyh-Chiang Shen Dr. Paul A. Kohl
School of Electrical and Computer School of Chemical and Biomolecular
Engineering Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. Chang-Ho Lee
Samsung RFIC Design Center

Date Approved: March 15, 2011
To dad, mom, and bro
ACKNOWLEDGEMENTS

I owe my deepest gratitude to my research advisor, Professor Gee-Kung Chang,
for his excellent guidance, his encouragement, his support, and his suggestions that
immensely improved this dissertation. I would also like to thank my committee members:
Professor Shyh-Chiang Shen for serving as the chair of my Ph.D. proposal exam,
Professor Geoffrey Ye Li, Professor Paul A. Kohl, and Dr. Chang-Ho Lee for their time
and invaluable suggestions. This dissertation would never have been possible without
their professional input.
I would like to express my gratitude to my former Ph.D. advisor, Dr. Joy Laskar,
for his support in my research project. This work would also not have been possible
without the mentorship and assistance from Dr. David Yeh. The past four years with the
Microwave Application Group (MAG) have been very productive thanks mainly to Dr.
Stephane Pinel, Dr. Bevin Perumana, Dr. Saikat Sarkar, Dr. Padmanava Sen, Dr.
Francesco Barale, Dr. Patrick Melet, Dr. Debasis Dawn, and Dr. Edward Gebara. I would
like to acknowledge the staff at the Georgia Electronic Design Center: Mrs. DeeDee
Bennett and Ms. Angelika Braig for their help. I also like to thank my wonderful past
present colleagues in the group: Arun Rachamadugu, Ashwin Muppalla, Gopal Iyer,
Shih-Chieh Hsin, Sen-Wen Hsiao, Matthew Leung, Eric Juntunen, Romain Pelard,
Nicolas Dudebout, Ming-Chun Lee, and the rest of MAG group for their contributions
related to my research.
iv
It is an honor for me to acknowledge Professor Mark Rodwell, Professor Kwang-
Ting (Tim) Cheng, and Professor Li Wang from the department of electrical and
computer engineering in the University of California Santa Barbara. I am thankful to be
exposed to the full range of engineering disciplines early at my career, which reinforce
and solidify my intense interest in electronic design and applications. Their influences
greatly stimulate my desire for advanced research in circuits, electronics, and digital
design methodologies.
I would like to take this opportunity to express my gratitude to my friends in
Atlanta for their support during my studies: Rung-Yu Tseng, Dr. Yu Tsao, Dr. Dau-
Cheng Lyu, Kelvin Chen-Chih Peng, John Chung-Hang Poh, and Yan-Yu Huang.
Last but not least, I am indebted to my father, Kuang-Hong Chuang, my mother,
Chiu-Hua Hsu, and my elder brother, Mike Yi-Cheng Chuang, for their unwavering love
in all of my endeavors. My immeasurable motivation and determination are driven by
their encouragement and sacrifices, which strive me to reach to this point of my life. As a
small token of my appreciation, I dedicate this dissertation to them.
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TABLE OF CONTENTS

ACKNOWLEDGEMENTS iv 
LIST OF TABLES xi 
LIST OF FIGURES xiii 
LIST OF ABBREVIATIONS xix 
SUMMARY xxii 
1.  INTRODUCTION 1 
1.1  Motivation 1 
1.2  Challenges 3 
1.3  Organization of the Dissertation 11 
2.  MILLIMETER-WAVE COMMUNICATION SYSTEMS 14 
2.1  Introduction 14 
2.2  Current Technologies Overview 14 
2.2.1  60 GHz Band 15 
2.2.1.1  Short-Distance Wireless Applications 15 
2.2.1.2  Channel Characteristics 16 
2.2.1.3  Channel Considerations 19 
2.2.2  70-80-90 GHz Band 21 
2.2.2.1  Channel Characteristics 21 
2.2.2.2  Channel Considerations 21 
2.2.2.3  Millimeter-Wave Applications 22 
2.2.3  Summary 23 
2.3  Wireless Receivers 25 
2.3.1  Homodyne Receivers 25 
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2.3.2  Heterodyne Receivers 27 
2.3.3  State-of-the-Art 60 GHz CMOS Front-End 30 
2.3.4  Example of 60 GHz Link Budget Analysis 31 
2.4  Digital Modulation Schemes 34 
2.4.1  CMOS Front-End Performance Limitations 34 
2.4.2  Amplitude-Shift Keying 37 
2.4.3  Phase-Shift Keying 38 
2.4.4  Quadrature Amplitude Modulation 42 
2.4.5  Orthogonal Frequency-Division Multiplexing 43 
2.5  Summary 46 
3.  ANALOG-TO-DIGITAL CONVERTERS 49 
3.1  Introduction 49 
3.2  High-Speed ADC Architectures 49 
3.2.1  Full Parallel (Flash) ADC 50 
3.2.2  Interpolating ADC 52 
3.2.3  ADC Architectures Comparison 54 
3.3  Fundamental Limits to Performance 55 
3.3.1  Periodic Sampling 55 
3.3.2  Quantization Noise 58 
3.3.3  Thermal Noise 60 
3.3.4  Aperture Jitter 62 
3.3.5  Comparator Design Consideration 65 
3.3.6  Capacitive Loading and Resistor Bowing 68 
3.4  State-of-the-Art CMOS A/D Converters 69 
3.5  Summary 72 
4.  APPLICATION-SPECIFIC IC DESIGN FLOW 74 
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4.1  Introduction 74 
4.2  Digital Front-End Design 74 
4.2.1  Digital Front-End Design Flow 75 
4.2.2  Digital Synthesis Flow 77 
4.2.3  Static Timing Analysis 78 
4.3  Digital Back-End Design 80 
4.3.1  Floorplanning 81 
4.3.2  Placement 82 
4.3.3  Clock Tree Synthesis 82 
4.3.4  Routing and Optimization 83 
4.4  Summary 84 
5.  LOW-POWER COHERENT BPSK DEMODULATOR 85 
5.1  Introduction 85 
5.2  Low-Power 3-bit Flash A/D Converter 85 
5.2.1  ADC Architecture 86 
5.2.2  High-Speed Optimizations 89 
5.2.2.1  Comparator Optimization 89 
5.2.2.2  Data Path Optimization 91 
5.2.3  Measurement Results 92 
5.3  Coherent BPSK Demodulator 97 
5.3.1  Theory of Operation 98 
5.3.2  Linear Model 103 
5.3.3  System Simulation 107 
5.3.4  Demodulator Architecture 111 
5.3.5  Circuit Implementation 113 
5.3.5.1  Quadrature Controlled-Voltage Oscillator 113 
viii
5.3.5.2  Double-Balance Passive Mixer 117 
5.3.5.3  Baseband Amplifiers 118 
5.3.5.4  Digital-to-Analog Converter 121 
5.3.5.5  Error Amplifier and Loop Filter 122 
5.4  Measurement Setup 123 
5.5  Measurement Results 124 
5.6  Summary 129 
6.  HIGH-PERFORMANCE DUAL-MODE DEMODULATOR 131 
6.1  Introduction 131 
6.2  High-Performance 3-bit Flash A/D Converter 131 
6.2.1  Architecture 131 
6.2.2  Track-and-Hold Circuit 134 
6.2.2.1  Design Considerations 134 
6.2.2.2  DC Offset Correction 137 
6.2.3  Preamplifier Stage 139 
6.2.3.1  Design Considerations 139 
6.2.3.2  Programmable Bias Control 141 
6.2.4  Comparators Design 142 
6.2.5  Resistor Averaging Network 145 
6.2.5.1  Offset Averaging Network as Spatial Filter 145 
6.2.5.2  Boundary Effect and Termination 150 
6.2.5.3  Speed Improvement 154 
6.2.6  Random Offset Reduction Analysis 156 
6.2.7  Digital Back-End 160 
6.2.8  Performance Summary 161 
6.3  Dual-Mode Multi-Gigabit Mixed-Signal Demodulator 165 
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6.3.1  Non-Coherent ASK Demodulator 166 
6.3.2  Coherent BPSK Demodulator 169 
6.3.2.1  Mode Select 170 
6.3.2.2  Error Amplifier 171 
6.3.2.3  QVCO Level Shifter 173 
6.4  Measurement Setup 174 
6.5  Measurement Results 175 
6.5.1  Non-Coherent ASK Results 176 
6.5.2  Coherent BPSK Results 178 
6.6  Summary 180 
7.  CONCLUSIONS 182 
7.1  Technical Contributions 182 
7.2  Conclusion and Future Work 185 
REFERENCES 188 
VITA 194 
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