Modern Digital Design and Switching Theory

485 Pages·2000·15.892 MB·English

by  Eugene D. Fabricius

Modem Digital Design
and
Switching Theory
Eugene D. Fabricius
California Polytechnic State University
San Luis Obispo, California
CRC Press
Boca Raton London New York Washington, D.C.
Library of Congress Cataloging-in-Publication Data
Fabricius, Eugene D.
Modern digital design and switching theory / by Eugene D. Fabricius.
p. cm.
Includes bibliographical references and index.
ISBN 0-8493-4212-0
1. Digital electronics. 2. Switching theory 3. System design.
I. Title.
TK7868 D5F33 1992
621.381'5—dc20 91-48255
CIP
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© 1992 by CRC Press LLC
No claim to original U.S. Government works
International Standard Book Number 0-8493-4212-0
Library of Congress Card Number 91-48255
Printed in the United States of America 5 6 7 8 9 0
Printed on acid-free paper
To Sherrie, Carol, and Brian,
inheritors of a digital world

CONTENTS
Prologue...........................................................................................................xi
Number Bases, Codes, and Binary Arithmetic..............................1
1.1 Introduction..............................................................................................1
1.2 Number Bases.........................................................................................2
1.3 Conversion of Binary, Quartemary, Octal, and
Hexadecimal Numbers...........................................................................6
1.4 Binary Arithmetic..................................................................................7
1. Binary Addition and Subtraction...................................................8
2. Binary Multiplication and Division...............................................8
1.5 Binary Codes...........................................................................................9
1. Binary Coded Decimal.....................................................................9
2. Binary Coded Decimal Addition.................................................10
3. Excess-Three Code........................................................................12
4. Error-Detecting Codes...................................................................12
5. Unit Distance Codes......................................................................13
6. Parity Checking...............................................................................14
7. The ASCII Code.............................................................................16
1.6 Boolean Cubes......................................................................................17
1.7 Complements.........................................................................................20
1. Logical or One’s Complement....................................................20
2. Two’s Complement........................................................................21
3. Nine’s and Ten’s Complement....................................................21
1.8 Modulo Arithmetic..............................................................................22
1.9 Binary Subtraction...............................................................................24
1, Subtraction Using One’s Complements.....................................24
2, Subtraction Using Two’s Complements.....................................25
1.10 Summary ................................................................................................28
Problems............................................................................................................30
Special Problems.............................................................................................32
Boolean Algebra and Implementation..............................................35
2.1 Introduction...........................................................................................35
2.2 Fundamental Boolean Operations....................................................36
2.3 Literals and Minterms.........................................................................38
2.4 Asserted and Not-Asserted Conditions and Truth Tables...........38
2.5 Conversion of Assertion Levels........................................................40
MODERN DIGITAL DESIGN AND SWITCHING THEORY
1. Ambipolar Notation and Positive Logic.....................................41
2. Ambipolar Notation and Negative Logic...................................41
3. The Inverter and Assertion Levels...............................................42
4. Mixed-Input Assertion Levels......................................................42
2.6 NAND and NOR Gates.......................................................................48
1. The NAND Gate..............................................................................48
2. The NOR Gate.................................................................................48
2.7 Functionally Complete Sets of Logic Gates...................................49
1. AND and INVERT Gates Only....................................................49
2. OR and INVERT Gates Only........................................................50
3. NAND Gates and NOR Gates......................................................50
2.8 DeMorgan’s Theorem..........................................................................50
2.9 Exclusive-OR and Exclusive-NOR Gates........................................53
2.10 Logical Operations on Binary Words...............................................54
2.11 Summary.................................................................................................55
Problems.............................................................................................................56
Special Problems...............................................................................................59
References...........................................................................................................59
Boolean Algebra and Circuit Realizations......................................61
3.1 Introduction.............................................................................................61
3.2 Huntington’s Postulates.......................................................................62
3.3 Proving Binary Boolean Theorems...................................................65
3.4 Two-Level Logic..................................................................................69
1. Sum-of-Products Form...................................................................70
2. Product-of-Sums Form....................................................................70
3. Realization of SOP and POS Forms...........................................71
3.5 Minterms and Maxterms......................................................................71
3.6 Two or More Functions.......................................................................74
3.7 Two-Level Gate Networks.................................................................75
1. Sum-of-Products Realizations of a Function............................75
2. Product-of-Sums Realizations of a Function.............................76
3.8 Shannon’s Expansion Theorem and Multilevel Logic.................79
3.9 Summary.................................................................................................84
Problems............................................................................................................86
Special Problems...............................................................................................89
References...........................................................................................................92
Mapping Boolean Expressions............................................................93
4.1 Introduction.............................................................................................93
4.2 Algebraic Simplification......................................................................94
4.3 Kamaugh-Map Simplification............................................................96
4.4 Prime Implicants....................................................................................99
1. Categories of Prime Implicants..................................................100
CONTENTS vii
4.5 Don’t Care Minterms.........................................................................106
4.6 Factoring on a Karnaugh Map.........................................................107
4.7 Variable-Entered Maps.....................................................................109
4.8 Cubes in n Dimensions.....................................................................Ill
4.9 Exclusive-OR and Exclusive-NOR Mapping................................115
4.10 Boolean Differences...........................................................................120
4.11 The Binary Adder..............................................................................122
4.12 Summary..............................................................................................126
Problems..........................................................................................................130
Special Problems............................................................................................135
References........................................................................................................138
5 Advanced Simplification Techniques.............................................139
5.1 Introduction.........................................................................................139
5.2 Karnaugh Maps for Five and Six Variables.................................140
5.3 The Quine-McCluskey Tabular Technique...................................143
1. Completely Specified Functions................................................144
2. Incompletely Specified Functions.............................................147
3. The Complementary Approach..................................................151
5.4 Multiple Outputs................................................................................153
1. Multiple Outputs by Karnaugh Mapping.................................154
2. Multiple Outputs by the Quine-McCluskey Method.............157
5.5 The Directed Search Algorithm.......................................................166
5.6 The Iterative Consensus Algorithm................................................171
5.7 The Generalized Iterative Consensus Algorithm.........................174
5.8 Summary..............................................................................................176
Problems..........................................................................................................177
Special Problems............................................................................................179
References........................................................................................................180
6 Multiplexers, Demultiplexers, ROMs, and PLDs........................181
6.1 Introduction.........................................................................................181
6.2 Multiplexers........................................................................................182
1. The Basic Multiplexer or Data Selector...................................183
2. Mapping and Multiplexer Design..............................................186
3. Multiplexers with Enable Inputs................................................188
6.3 AND-OR-INVERT Logic and Multiplexer Trees.......................190
6.4 Shannon’s Expansion Theorem and Multiplexer Design..........195
6.5 Truth-Table Partitioning for Multiplexer Design.........................203
6.6 Determination of Minimal Multiplexer Trees...............................205
6.7 Demultiplexers and Decoders..........................................................207
1. The Basic Demultiplexer or Decoder.......................................209
2. Demultiplexers with Enable Inputs..........................................212
3. The Decoder as a Function Generator......................................214
viii MODERN DIGITAL DESIGN AND SWITCHING THEORY
6.8 Priority Encoders................................................................................215
6.9 Read-Only Memory............................................................................217
6.10 Programmable Array Logic Devices..............................................223
1. The Programmable Read-Only Memory..................................225
2. The Programmable Logic Array.................................................226
3. Programmable Array Logic.........................................................232
6.11 Summary..............................................................................................233
Problems...........................................................................................................235
Special Problems............................................................................................239
References.........................................................................................................240
7 Latches and Flip-Flops...........................................................................241
7.1 Introduction..........................................................................................241
7.2 Basic Asynchronous Binary Latches..............................................242
1. The Active-High Asynchronous S-R Latch............................243
2. The Active-Low Asynchronous S-R Latch.............................248
7.3 The Clocked or Gated Latch............................................................250
1. The Clocked S-R Latch...............................................................251
2. The Gated Toggle Latch..............................................................255
3. The Gated J-K Latch.....................................................................257
4. The Gated Data Latch...................................................................259
7.4 The Flip-Flop.......................................................................................261
1. The Master/Slave S-R Flip-Flop................................................261
2. The Master/Slave J-K Flip-Flop.................................................261
3. The Master/Slave Data Flip-Flop..............................................265
4. The Master/Slave Toggle Flip-Flop..........................................265
7.5 The Edge-Triggered Flip-Flop..........................................................266
7.6 The J-K Flip-Flop with Data Lockout...........................................273
7.7 Direct Set and Reset Flip-Flops......................................................276
7.8 Summary..............................................................................................279
Problems...........................................................................................................281
Special Problems............................................................................................290
References........................................................................................................293
8 Counters and Registers.........................................................................295
8.1 Introduction..........................................................................................295
8.2 Binary Counters..................................................................................296
1. Asynchronous Binary Counters..................................................297
2. Synchronous Binary Counters....................................................298
8.3 Designing Synchronous Counters...................................................298
8.4 Lockout.................................................................................................310
8.5 Serial and Parallel Carry Synchronous Counters.........................214
8.6 Programmable Ripple Counters.......................................................317
8.7 Binary Shift Registers........................................................................323
CONTENTS ix
8.8 Summary..............................................................................................329
Problems..........................................................................................................330
Special Problems............................................................................................339
References........................................................................................................340
9 Application-Specific Integrated Circuits.......................................341
9.1 Introduction.........................................................................................341
9.2 General PLA Considerations...........................................................342
1. PLA Input Decoding....................................................................344
2. Registered PLDs............................................................................346
9.3 Programming the PLA......................................................................351
9.4 Dynamic Logic Arrays.....................................................................352
9.5 The Finite-State Machine as a PLA Structure.............................353
9.6 Reduction of Customized PL As......................................................358
9.7 PLA Folding........................................................................................360
9.8 Multilevel Logic Structures.............................................................368
9.9 Field Programmable Gate Arrays...................................................371
1. Table-Look-Up Architecture.......................................................372
2. Multiplexer Architecture.............................................................379
3. The Multilevel NAND Structure...............................................380
9.10 Summary..............................................................................................389
Problems..........................................................................................................391
Special Problems............................................................................................395
References........................................................................................................396
10 Multilevel Minimization..........................................................................397
10.1 Introduction.........................................................................................397
10.2 Factoring Boolean Expressions.......................................................397
10.3 Decomposition and Extraction Techniques...................................398
10.4 Division of Switching Functions....................................................406
10.5 Algebraic Division.............................................................................407
1. Weak Division...............................................................................408
2. Iterative Weak Division..............................................................410
10.6 Boolean Division...............................................................................411
10.7 Kernels and Co-Kernels of an Expression....................................412
1. Kernel Determination by Tabular Means................................414
2. Kernel Determination by Rectangle Covering........................415
10.8 Boolean Trees.....................................................................................419
1. Tree Mapping by Kernel Extraction.........................................420
2. Tree Mapping by Shannon’s Theorem.....................................421
10.9 The Berkeley ESPRESSO Program...............................................422
10.10 Binary Decision Diagrams and Directed Acyclic Graphs.........426
1. The Ordered Binary Decision Diagram....................................426
2. Inversion and Reduced Binary Decision Diagrams...............427