MIPI Alliance Specification for D-PHY

121 Pages·2012·0.97 MB·English

5-Jan-2012

®
MIPI Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011

* NOTE TO IMPLEMENTERS *
This document is a MIPI Specification. MIPI member companies’ rights and obligations apply to
this MIPI Specification as defined in the MIPI Membership Agreement and MIPI Bylaws.
However, implementers should be aware of the following:
It is the good faith expectation of the MIPI PHY Working Group that D-PHY v1.1 is stable and
robust. The MIPI Alliance currently recommends that any member companies considering
implementation of D-PHY base their work on this version of the Specification (v1.1), which is
intended to supersede the previous version (v1.00.00).
This version of the Specification includes minor relaxations to the conformance ranges for several
key parameters. These modifications are intended to ease implementation for designs supporting
HS bitrates > 1 Gbps, allowing for slightly greater conformance margins for these parameters, to
better allow for process and manufacturing variations in these implementations.
In some cases the modified conformance limits apply only to operation at HS rates > 1 Gbps
(while the previous limits still apply to rates ≤ 1Gbps), while in other cases the new conformance
values are applicable to all HS rates. In all cases, the modified conformance limits have been
widened with respect to the previous values, so that any implementation conformant to these
parameters in the previous version of this Specification (v1.00.00) should also be conformant to
the modified limits defined in this version (v1.1).
The follow list includes all parameters with modified conformance limits:
• HS rise/fall time (t , t )
R F
• VOD mismatch (ΔV )
OD
• TX data to clock skew (T )
SKEW[TX]
• RX setup and hold times (T , T )
SETUP[RX] HOLD[RX]
• TX and RX return loss (Sdd , Sdd )
TX RX
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5-Jan-2012
See the respective Specification sections for details.
Also in this version of the Specification, one new parameter has been added (∆UI) that more
precisely constrains the allowed peak-to-peak variation of the HS bitrate (UI) within a single HS
burst. The addition of this new parameter is intended to address suspected interoperability
concerns that may arise for devices that show excessive variability of their HS-TX bitrate within a
single HS burst.
It is the good faith expectation of the MIPI PHY WG that there will be no significant functional
changes to the fundamental technology described in this Specification.

Copyright © 2012 MIPI Alliance, Inc. All rights reserved.
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY

®
MIPI Alliance Specification for
D-PHY
Version 1.1 – 7 November 2011
MIPI Board Approved 16-Dec-2011
Further technical changes to this document are expected as work continues in the PHY Working Group
Copyright © 2007-2011 MIPI Alliance, Inc. All rights reserved.
MIPI Alliance Member Confidential.
Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
1 NOTICE OF DISCLAIMER
2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or
3 controlled by any of the authors or developers of this material or MIPI®. The material contained herein is
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
Contents
41
42 Version 1.1 – 7 November 2011 ................................................................................................................ i
43 1 Introduction .................................................................................................................................... 10
44 1.1 Scope ...................................................................................................................................... 10
45 1.2 Purpose ................................................................................................................................... 11
46 2 Terminology ................................................................................................................................... 12
47 2.1 Definitions .............................................................................................................................. 12
48 2.2 Abbreviations .......................................................................................................................... 13
49 2.3 Acronyms ............................................................................................................................... 13
50 3 References ...................................................................................................................................... 16
51 4 D-PHY Overview ............................................................................................................................ 17
52 4.1 Summary of PHY Functionality............................................................................................... 17
53 4.2 Mandatory Functionality ......................................................................................................... 17
54 5 Architecture .................................................................................................................................... 18
55 5.1 Lane Modules ......................................................................................................................... 18
56 5.2 Master and Slave..................................................................................................................... 19
57 5.3 High Frequency Clock Generation........................................................................................... 19
58 5.4 Clock Lane, Data Lanes and the PHY-Protocol Interface ......................................................... 19
59 5.5 Selectable Lane Options .......................................................................................................... 20
60 5.6 Lane Module Types ................................................................................................................. 22
61 5.6.1 Unidirectional Data Lane ................................................................................................. 23
62 5.6.2 Bi-directional Data Lanes ................................................................................................ 23
63 5.6.3 Clock Lane ...................................................................................................................... 24
64 5.7 Configurations ........................................................................................................................ 24
65 5.7.1 Unidirectional Configurations.......................................................................................... 26
66 5.7.2 Bi-Directional Half-Duplex Configurations...................................................................... 28
67 5.7.3 Mixed Data Lane Configurations ..................................................................................... 29
68 6 Global Operation ............................................................................................................................ 30
69 6.1 Transmission Data Structure ................................................................................................... 30
70 6.1.1 Data Units ....................................................................................................................... 30
71 6.1.2 Bit order, Serialization, and De-Serialization ................................................................... 30
72 6.1.3 Encoding and Decoding ................................................................................................... 30
73 6.1.4 Data Buffering ................................................................................................................. 30
74 6.2 Lane States and Line Levels .................................................................................................... 30
75 6.3 Operating Modes: Control, High-Speed, and Escape ............................................................... 31
76 6.4 High-Speed Data Transmission ............................................................................................... 32
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
77 6.4.1 Burst Payload Data .......................................................................................................... 32
78 6.4.2 Start-of-Transmission ...................................................................................................... 32
79 6.4.3 End-of-Transmission ....................................................................................................... 33
80 6.4.4 HS Data Transmission Burst ............................................................................................ 33
81 6.5 Bi-directional Data Lane Turnaround ...................................................................................... 35
82 6.6 Escape Mode ........................................................................................................................... 38
83 6.6.1 Remote Triggers .............................................................................................................. 39
84 6.6.2 Low-Power Data Transmission ........................................................................................ 40
85 6.6.3 Ultra-Low Power State ..................................................................................................... 40
86 6.6.4 Escape Mode State Machine ............................................................................................ 40
87 6.7 High-Speed Clock Transmission ............................................................................................. 42
88 6.8 Clock Lane Ultra-Low Power State ......................................................................................... 47
89 6.9 Global Operation Timing Parameters ...................................................................................... 49
90 6.10 System Power States................................................................................................................ 53
91 6.11 Initialization ........................................................................................................................... 53
92 6.12 Calibration .............................................................................................................................. 53
93 6.13 Global Operation Flow Diagram ............................................................................................. 53
94 6.14 Data Rate Dependent Parameters (informative) ....................................................................... 55
95 6.14.1 Parameters Containing Only UI Values ........................................................................... 56
96 6.14.2 Parameters Containing Time and UI values ..................................................................... 56
97 6.14.3 Parameters Containing Only Time Values ....................................................................... 56
98 6.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent ................ 57
99 7 Fault Detection ............................................................................................................................... 58
100 7.1 Contention Detection .............................................................................................................. 58
101 7.2 Sequence Error Detection ........................................................................................................ 58
102 7.2.1 SoT Error ........................................................................................................................ 59
103 7.2.2 SoT Sync Error ................................................................................................................ 59
104 7.2.3 EoT Sync Error ............................................................................................................... 59
105 7.2.4 Escape Mode Entry Command Error ............................................................................... 59
106 7.2.5 LP Transmission Sync Error ............................................................................................ 59
107 7.2.6 False Control Error .......................................................................................................... 59
108 7.3 Protocol Watchdog Timers (informative)................................................................................. 59
109 7.3.1 HS RX Timeout ............................................................................................................... 59
110 7.3.2 HS TX Timeout ............................................................................................................... 59
111 7.3.3 Escape Mode Timeout ..................................................................................................... 60
112 7.3.4 Escape Mode Silence Timeout ......................................................................................... 60
113 7.3.5 Turnaround Errors ........................................................................................................... 60
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
114 8 Interconnect and Lane Configuration .............................................................................................. 61
115 8.1 Lane Configuration ................................................................................................................. 61
116 8.2 Boundary Conditions .............................................................................................................. 61
117 8.3 Definitions .............................................................................................................................. 61
118 8.4 S-parameter Specifications ...................................................................................................... 62
119 8.5 Characterization Conditions .................................................................................................... 62
120 8.6 Interconnect Specifications...................................................................................................... 63
121 8.6.1 Differential Characteristics .............................................................................................. 63
122 8.6.2 Common-mode Characteristics ........................................................................................ 64
123 8.6.3 Intra-Lane Cross-Coupling .............................................................................................. 64
124 8.6.4 Mode-Conversion Limits ................................................................................................. 64
125 8.6.5 Inter-Lane Cross-Coupling .............................................................................................. 64
126 8.6.6 Inter-Lane Static Skew .................................................................................................... 65
127 8.7 Driver and Receiver Characteristics ........................................................................................ 65
128 8.7.1 Differential Characteristics .............................................................................................. 65
129 8.7.2 Common-Mode Characteristics ........................................................................................ 66
130 8.7.3 Mode-Conversion Limits ................................................................................................. 66
131 8.7.4 Inter-Lane Matching ........................................................................................................ 66
132 9 Electrical Characteristics ................................................................................................................ 67
133 9.1 Driver Characteristics ............................................................................................................. 68
134 9.1.1 High-Speed Transmitter .................................................................................................. 68
135 9.1.2 Low-Power Transmitter ................................................................................................... 73
136 9.2 Receiver Characteristics .......................................................................................................... 77
137 9.2.1 High-Speed Receiver ....................................................................................................... 77
138 9.2.2 Low-Power Receiver ........................................................................................................ 79
139 9.3 Line Contention Detection ...................................................................................................... 80
140 9.4 Input Characteristics ............................................................................................................... 81
141 10 High-Speed Data-Clock Timing .................................................................................................. 83
142 10.1 High-Speed Clock Timing ....................................................................................................... 83
143 10.2 Forward High-Speed Data Transmission Timing ..................................................................... 84
144 10.2.1 Data-Clock Timing Specifications ................................................................................... 85
145 10.3 Reverse High-Speed Data Transmission Timing...................................................................... 86
146 11 Regulatory Requirements ............................................................................................................ 88
147 Annex A Logical PHY-Protocol Interface Description (informative) ................................................... 89
148 A.1 Signal Description .................................................................................................................. 89
149 A.2 High-Speed Transmit from the Master Side............................................................................. 96
150 A.3 High-Speed Receive at the Slave Side...................................................................................... 97
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
151 A.4 High-Speed Transmit from the Slave Side ............................................................................... 97
152 A.5 High-Speed Receive at the Master Side ................................................................................... 98
153 A.6 Low-Power Data Transmission................................................................................................ 98
154 A.7 Low-Power Data Reception ..................................................................................................... 99
155 A.8 Turn-around............................................................................................................................ 99
156 Annex B Interconnect Design Guidelines (informative) .....................................................................101
157 B.1 Practical Distances .................................................................................................................101
158 B.2 RF Frequency Bands: Interference ..........................................................................................101
159 B.3 Transmission Line Design......................................................................................................101
160 B.4 Reference Layer .....................................................................................................................102
161 B.5 Printed-Circuit Board .............................................................................................................102
162 B.6 Flex-foils................................................................................................................................102
163 B.7 Series Resistance ....................................................................................................................102
164 B.8 Connectors .............................................................................................................................102
165 Annex C 8b9b Line Coding for D-PHY (normative) ..........................................................................103
166 C.1 Line Coding Features .............................................................................................................104
167 C.1.1 Enabled Features for the Protocol ...................................................................................104
168 C.1.2 Enabled Features for the PHY .........................................................................................104
169 C.2 Coding Scheme ......................................................................................................................104
170 C.2.1 8b9b Coding Properties...................................................................................................104
171 C.2.2 Data Codes: Basic Code Set ............................................................................................105
172 C.2.3 Comma Codes: Unique Exception Codes ........................................................................106
173 C.2.4 Control Codes: Regular Exception Codes ........................................................................106
174 C.2.5 Complete Coding Scheme ...............................................................................................107
175 C.3 Operation with the D-PHY .....................................................................................................107
176 C.3.1 Payload: Data and Control ..............................................................................................107
177 C.3.2 Details for HS Transmission ...........................................................................................107
178 C.3.3 Details for LP Transmission ...........................................................................................108
179 C.4 Error Signaling ......................................................................................................................108
180 C.5 Extended PPI .........................................................................................................................109
181 C.6 Complete Code Set .................................................................................................................110
182
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
Figures
183
184 Figure 1 Universal Lane Module Functions ............................................................................................ 18
185 Figure 2 Two Data Lane PHY Configuration .......................................................................................... 20
186 Figure 3 Option Selection Flow Graph ................................................................................................... 21
187 Figure 4 Universal Lane Module Architecture ........................................................................................ 22
188 Figure 5 Lane Symbol Macros and Symbols Legend ............................................................................... 25
189 Figure 6 All Possible Data Lane Types and a Basic Unidirectional Clock Lane ....................................... 26
190 Figure 7 Unidirectional Single Data Lane Configuration ........................................................................ 27
191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT .............................................. 27
192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT ........................... 28
193 Figure 10 Bidirectional Single Data Lane Configuration ........................................................................ 28
194 Figure 11 Bi-directional Multiple Data Lane Configuration .................................................................... 29
195 Figure 12 Mixed Type Multiple Data Lane Configuration ...................................................................... 29
196 Figure 13 Line Levels ............................................................................................................................. 31
197 Figure 14 High-Speed Data Transmission in Bursts ................................................................................ 33
198 Figure 15 TX and RX State Machines for High-Speed Data Transmission .............................................. 34
199 Figure 16 Turnaround Procedure ............................................................................................................ 36
200 Figure 17 Turnaround State Machine ..................................................................................................... 37
201 Figure 18 Trigger-Reset Command in Escape Mode ............................................................................... 39
202 Figure 19 Two Data Byte Low-Power Data Transmission Example ........................................................ 40
203 Figure 20 Escape Mode State Machine ................................................................................................... 41
204 Figure 21 Switching the Clock Lane between Clock Transmission and Low-Power Mode....................... 44
205 Figure 22 High-Speed Clock Transmission State Machine ...................................................................... 46
206 Figure 23 Clock Lane Ultra-Low Power State State Machine .................................................................. 47
207 Figure 24 Data Lane Module State Diagram ........................................................................................... 54
208 Figure 25 Clock Lane Module State Diagram ......................................................................................... 55
209 Figure 26 Point-to-point Interconnect ..................................................................................................... 61
210 Figure 27 Set-up for S-parameter Characterization of RX, TX and TLIS ................................................ 62
211 Figure 28 Template for Differential Insertion Losses .............................................................................. 63
212 Figure 29 Template for Differential Reflection at Both Ports .................................................................. 63
213 Figure 30 Inter-Lane Common-mode Cross-Coupling Template ............................................................. 64
214 Figure 31 Inter-Lane Differential Cross-Coupling Template ................................................................... 65
215 Figure 32 Differential Reflection Template for Lane Module Receivers .................................................. 65
216 Figure 33 Differential Reflection Template for Lane Module Transmitters ............................................. 66
217 Figure 34 Template for RX Common-Mode Return Loss ........................................................................ 66
218 Figure 35 Electrical Functions of a Fully Featured D-PHY Transceiver .................................................. 67
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Version 1.1 7-Nov-2011 MIPI Alliance Specification for D-PHY
219 Figure 36 D-PHY Signaling Levels ........................................................................................................ 68
220 Figure 37 Example HS Transmitter ........................................................................................................ 69
221 Figure 38 Ideal Single-ended and Resulting Differential HS Signals ....................................................... 70
222 Figure 39 Possible ΔV and ΔV Distortions of the Single-ended HS Signals .................................. 71
CMTX OD
223 Figure 40 Example Circuit for V and V Measurements ................................................................ 71
CMTX OD
224 Figure 41 Example LP Transmitter ........................................................................................................ 73
225 Figure 42 V-I Characteristic for LP Transmitter Driving Logic High ...................................................... 73
226 Figure 43 V-I Characteristic for LP Transmitter Driving Logic Low....................................................... 74
227 Figure 44 LP Transmitter V-I Characteristic Measurement Setup ........................................................... 74
228 Figure 45 Slew Rate vs. C (Falling Edge) ........................................................................................ 76
LOAD
229 Figure 46 Slew Rate vs. C (Rising Edge) ......................................................................................... 77
LOAD
230 Figure 47 HS Receiver Implementation Example .................................................................................... 77
231 Figure 48 Input Glitch Rejection of Low-Power Receivers ...................................................................... 79
232 Figure 49 Signaling and Contention Voltage Levels ............................................................................... 80
233 Figure 50 Pin Leakage Measurement Example Circuit ........................................................................... 81
234 Figure 51 Conceptual D-PHY Data and Clock Timing Compliance Measurement Planes ....................... 83
235 Figure 52 DDR Clock Definition ............................................................................................................ 84
236 Figure 53 Data to Clock Timing Definitions ........................................................................................... 85
237 Figure 54 Conceptual View of HS Data Transmission in Reverse Direction ............................................ 86
238 Figure 55 Reverse High-Speed Data Transmission Timing at Slave Side ................................................ 87
239 Figure 56 Example High-Speed Transmission from the Master Side ....................................................... 97
240 Figure 57 Example High-Speed Receive at the Slave Side ...................................................................... 97
241 Figure 58 Example High-Speed Transmit from the Slave Side ................................................................ 98
242 Figure 59 Example High-Speed Receive at the Master Side .................................................................... 98
243 Figure 60 Low-Power Data Transmission ............................................................................................... 99
244 Figure 61 Example Low-Power Data Reception ...................................................................................... 99
245 Figure 62 Example Turn-around Actions Transmit-to-Receive and Back to Transmit ........................... 100
246 Figure 63 Line Coding Layer ................................................................................................................ 103
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