Microprocessing and Microprogramming 1991: Vol 31 Index

3 Pages·1991·0.31 MB·English

Microprocessing and Microprogramming 31 (1991) 145-146
North-Holland
Author index of volume 31 (1991)
Ahmed, H., A dataflow model based on a vector Larsson, M., Mixed static and dynamic reasoning in a
queueing scheme 90 formal system
Antola, A. and M. Tellarini, Definition and evaluation of Lee, A.S.C., see Milligan, P.
a transputer-based architecture for image compression Lins, R.D., see Musicante, M.A.
and reconstruction 127
Mahnié, V., Using grid files for a relational database
Birbas, M.K., see Soudris, D.J. 53 management system
Biswas, P., see Dewan, G. 105 Milligan, P., L.C. Waring and A.S.C. Lee, BIFS: a filing
system for multiprocessor based systems
Choi, J.H., see Etkin, J. Moon, S.C., see Shin, D.C.
Cizek, N., see Dreo, G. Musicante, M.A. and R.D. Lins, GM-C: a graph multi-
combinator machine
Dewan, G. and P. Biswas, A snooping cache coherency
Orhun, E., see Tunaili, S.
protocol for hierarchically organized multiprocessors 105
Dreo, G., N. Cizek, B. Horvat and V. Zumer, Cost
analysis of interconnection networks 77 Papp, Z., Schedular architecture for knowledge based
measuring systems
Peng, Z., Design of clocking schemes in high-level
Etkin, J. and J.H. Choi, Architecture and implementation
synthesis
method of real-time recovery in distributed systems 113
Perotto, J-F., C. Piguet and A. Kagi, Multiprocess
architecture for watch applications
Fjellborg, B., A Petri net model for pipeline scheduling 121
Piquet, C., see Perotto, J-F.
Flavell, S., S. Winter and D. Wilson, Matching region
Piuri, V. and R. Stefanelli, Concurrent error detection in
adjacency graphs
parallel multipliers and complex arithmetic structures:
Furuya, T., see Higuchi, T.
remarks on the use of the SN code
Ghisotti, P. and A. Zanna, New techniques in mapping Roxman, |., see GyOrkos, J.
applications on transputer networks
Goutis, C.E., see Soudris, D.J.
Shin, D.C. and S.C. Moon, An efficient log-based crash
Gyorkés, J., |. Rozman and T. Welzer, Activation and
recovery for nested transactions
validation of the system specifications
Signorini, J., Integrated design tools for very large scale
cellular architectures
Handa, K., see Higuchi, T. Soudris, D.J., M.K. Birbas and C.E. Goutis, Mapping
Harms, E., S. Kounias, L.J. Vroomen and P.J. Zsombor- iterative algorithms on regular processor arrays without
Murray, A binary decision/transputer network for the using uniform recurrent equations 53
control of a planar three degree of freedom parallel Stainov, R., An asynchronous checkpointing service 117
robotic manipulator Stefanelli, R., see Piuri, V. 47
Higuchi, T., T. Furuya, K. Handa and A. Kokubu, Initial
evaluation of a parallel associative processor IXM2 Tellarini, M., see Antola, A.
Horvat, B., see Cieo, G. Tsoutsou, K., see Tziallas, G.D. 25
Tunali, S. and E. Orhun, A prototype rule-based system
Kagi, A., see Perotto, J-F. to schedule production for a job-shop 19
Karkanis, S., see Tziallas, G.D. Tziallas, G.D., S. Karkanis and K. Tsoutsou, A
Kokubu, A., see Higuchi, T. knowledge-based approach for the development of
Kounias, S., see Harms, E. concurrent software 25
Kozlowski, W.E., Hybrid fault diagnosability using the
comparison-based approach Vroomen, L.J., see Harms, E.
146 Author index of volume 31
Waring, L.C., see Milligan, P. Zanna, A., see Chisotti, P.
Weizer, T., see Gyorkés, J. Zsombor-Murray, P.J., see Harms, E.
Wilson, D., see Flavell, S. Zumer, V., see Dreo, G.
Winter, S., see Flavell, S.
Microprocessing and Microprogramming 31 (1991) 147
North-Holland
Subject index of volume 31 (1991)
Algorithm mapping Lazy functional languages
Applications mapping Log sequence numbers
Associative memory
Associative parallel processor MIMD machines
Multiprocessor architecture
BIFS
Binary decision/transputer network Nested transactions
Cache coherency Occam
Cellular automata
Checkpointing service Parallel multipliers
Clocking schemes design Petri net
Concurrent software Pipelining
Cost analysis Process farming
Cost formulae Processor architecture
Prolog
Data compression
Dataflow Quantization
Discrete cosine transform Query evaluation
Disk access
Real-time
Error detection Real-time environment
Recovery mechanism
Fault diagnosis Region adjacency graphs
Regular array architecture
Graph multi-combinators Robotic manipulator
Grid directory Rule-based approach
Hardware analysis Schedular architecture
Heuristics Search region
Hierarchically organized multiprocessor Semantic network
High-level synthesis SIMD arrays
Huffman coding Symbolic computation
System specifications
Interconnection networks
Vector processor
Job-shop
Join Watch integrated circuits