Microelectronics Failure Analysis Desk Reference

685 Pages·2011·43.402 MB·English

by  Ross, Richard J.(eds.)

Microelectronics
Failure Analysis

_____________________________

Desk Reference
Sixth Edition
_____________________________

Edited by
Richard J. Ross

Published by
ASM International®
Materials Park, Ohio 44073-0002
www.asminternational.org
Copyright (cid:2) 2011
by
ASM International®
All rights reserved

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First printing, October 2011

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ISBN-13: 978-1-61503-725-4
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ASM International®
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Printed in the United States of America
Preface to the Sixth Edition

Richard J. Ross, Editor-in-Chief

As the semiconductor industry moves from the No undertaking of this magnitude is
“micro” to the “nano” realm, the Failure accomplished without the efforts of many. The
Analysis community needs to be pro-active in Editorial Board and Section Champions
maintaining its ability to verify, isolate, recruited experts in the various specialized
uncover, and identify the root-cause of fields, nurtured and encouraged them, and drove
problems. These problems may be discovered to a schedule which, in the economic climate of
in design debug, product or technology the past few years, required understanding and
development and qualification, fabrication, revision. The staff at ASM International,
packaging, reliability stress, or, most particularly Kate Russell and Scott Henry were
unfortunately, in the field. New materials and of immeasurable help and support. Thomas
ever-shrinking technology dimensions make it Zanon, EDFAS Education Chair, was tolerant,
increasingly more challenging for the failure understanding, and supportive when the
analyst and make it increasingly important to inevitable frustrations of time and effort
provide analysis with information, training, appeared. Without the various authors, of
equipment, and materials to enable them to cope course, this work does not exist and I am
with these challenges and opportunities. eternally grateful to each of them. Finally, I
want to thank my family for their support for the
For over three decades, this work, time spent on the computer and the phone.
“Microelectronics Failure Analysis Desk
Reference” has been a key aide to analysts. It
has been used as a textbook, a workbook, and a
laboratory manual over that time and has
undergone, now, six iterations of content
selection and revision. The printed version has
gone from 275 pages to over 600. Some of the
methods and techniques which are included in
this edition did not even exist when the first
edition was published in the 1970s.

The work itself must change as well to reflect
the challenges and opportunities of the times.
This edition will exist in web-based online,
DVD, and printed form to meet the diverse
needs of the community. Some “old favorites”
remain as their base technology and practice are
still relevant and useful; others have become
superseded by the technology. The use of color

throughout the work is also introduced in this
edition.

xi
Contents

Preface to the Sixth Edition....................................................................................................xi

Section 1: Introduction

The Failure Analysis Process..................................................................................................1
M. Steven Ferrier

Section 2: Failure Analysis Process Overviews

System Level Failure Analysis Process: Making Failure Analysis a Value Add
Proposition in Today’s High Speed Low Cost PC Environment .......................................16
Michael Lane, Roger Bjork, Jeff Birdsley

Board Level Failure Mechanisms and Analysis in
Hand-Held Electronic Products.............................................................................................23
Sridhar Canumalla, Puligandla Viswanadham

Failure Analysis Flow for Package Failures.........................................................................34
Rajen Dias

Chip-Scale Packages and Their Failure Analysis Challenges .........................................40
Susan Xia Li

Wafer Level Failure Analysis Process Flow.........................................................................49
J.H. Lee, Y.S. Huang, D.H. Su

Failure Analysis of Microelectromechanical Systems (MEMS)..........................................52
Jeremy A. Walraven, Bradley A. Waterson, Ingrid De Wolf

Failure Analysis and Reliability of Optoelectronic Devices ...............................................78
Robert W. Herrick

Solar Photovoltaic Module Failure Analysis........................................................................99
G.B. Alers

DRAM Failure Analysis and Defect Localization Techniques ..........................................104
Martin Versen

Failure Analysis of Passive Components ..........................................................................111
Stan Silvus

v
Section 3: Failure Analysis Topics

Reliability and Quality Basics for Failure Analysts ..........................................................121
Steven Hoffman, Chris Henderson

Electronics and Failure Analysis .......................................................................................128
Jerry Soden, Jaume Segura, Charles F. Hawkins

Submicron CMOS Devices ..................................................................................................149
Theodore A. Dellin

Analog Device and Circuit Characterization .....................................................................159
Steve Frank

Screening for Counterfeit Electronic Parts .......................................................................171
Bhanu Sood, Diganta Das

Section 4: Fault Verification and Classification

An Overview of Analog Design for Test and Diagnosis....................................................181
Stephen Sunter

An Overview of Integrated Circuit Testing Methods .........................................................190
Anne Gattiker, Phil Nigh, Rob Aitken

Diagnosis of Scan Logic and Diagnosis Driven Failure Analysis....................................199

Srikanth Venkataraman, Martin Keim, Geir Eide

Interpretation of Power DMOS Transistor Characteristics
Measured with Curve Tracer ...............................................................................................209
Hubert Beermann

High-Volume Scan Analysis: Methods to Avoid Failure Analysis ...................................218
Darrell Carder, Steve Palosh, Rajesh Raina

Differentiating between EOS and ESD Failures for ICs ....................................................225
Leo G. Henry

The Power of Semiconductor Memory Failure Signature Analysis .................................239
Cary A. Gloor

Section 5: Localization Techniques

Beam-Based Defect Localization Techniques ..................................................................246
Edward I. Cole, Jr.

Electron Beam Probing .......................................................................................................263
John T.L. Thong
v i
Failure Localization with Active and
Passive Voltage Contrast in FIB and SEM .......................................................................269
Ruediger Rosenkranz

Fundamentals of Photon Emission (PEM) in Silicon –
Electroluminescence for Analysis of Electronic Circuit and
Device Functionality ............................................................................................................279
Christian Boit

Picosecond Imaging Circuit Analysis – PICA ...................................................................292
D. Vallett

Current Imaging Using Magnetic Field Sensors ...............................................................301
L.A. Knauss, S.I. Woods, A. Orozco

Thermal Defect Detection Techniques ...............................................................................310
Daniel L. Barton, Paiboon Tangyunyong

Thermal Failure Analysis by IR Lock-In Thermography ...................................................330
O. Breitenstein, C. Schmidt, F. Altmann, D. Karg

Principles of Thermal Laser Stimulation Techniques ......................................................340
F. Beaudoin, R. Desplats, P. Perdu, C. Boit

Introduction to Laser Voltage Probing (LVP) of Integrated Circuits ...............................349
Siva Kolachina

CAD Navigation in FA and Design/Test Data for Fast Fault Isolation .............................354
William Ng

Acoustic Microscopy of Semiconductor Packages ..........................................................362
Cheryl D. Hartfield, Thomas M. Moore

Electronic Package Fault Isolation Using TDR .................................................................383
D. Smolyansky

Section 6: Deprocessing and Sample Preparation

Delayering Techniques: Dry Processes Wet Chemical Processing and
Parallel Lapping....................................................................................................................397
Kendall Scott Wills, Srikanth Perungulam

The Art of Cross Sectioning ...............................................................................................417
B. Engel, E. Levine, J. Petrus, A. Shore

Delineation Etching of Semiconductor Cross Sections ...................................................437
S. Roberts, D. Flatoff

vi i
Special Techniques for Backside Deprocessing ..............................................................440
Seth Prejean, Brennan Davis, Lowell Herlinger, Richard Johnson,
Renee Parente, Mike Santana

Deprocessing Techniques for Copper, Low K, and SOI Devices ....................................445
Huixian Wu, James Cargo

Section 7: Inspection

Optical Microscopy .............................................................................................................457
John McDonald

Scanning Electron Microscopy ..........................................................................................477
W. Vanderlinde

Ultra-High Resolution in the Scanning Electron Microscope ..........................................497
W. Vanderlinde

Transmission Electron Microscopy for
Failure Analysis of Semiconductor Devices......................................................................506
Swaminathan Subramanian, Raghaw S. Rai

X-ray Imaging Tools for Electronic Device Failure Analysis ...........................................529
Steve Wang

Atomic Force Microscopy: Modes and Analytical Techniques with
Scanning Probe Microscopy ..............................................................................................536
J. Colvin, K. Jarausch

Section 8: Materials Analysis

Energy Dispersive X-ray Analysis ......................................................................................549
W. Vanderlinde

Analysis of Submicron Defects by Auger Electron Spectroscopy (AES)........................561
Juergen Scherer, Patrick Schnabel, Kenton Childs

SIMS Solutions for Next Generation IC Processes and Devices......................................573
Gary Mount, Yung Liou, Han-Chung Chien

Section 9: Focused Ion Beam Applications

Focused Ion Beam (FIB) Systems: A Brief Overview........................................................583
Kultaransingh (Bobby) Hooghan, Richard J. Young

Circuit Edit at First Silicon ..................................................................................................594
Ted Lundquist, Mark Thompson
vi ii
The Process of Editing Circuits through the Bulk Silicon ...............................................607
Nicholas Antoniou

Section 10: Management and Reference Information

Education and Training for the Analyst .............................................................................612
Christopher L. Henderson

Management Principles and Practices for the Failure Analysis Laboratory ..................617
Richard J. Ross

Managing the Unpredictable – A Business Model for Failure Analysis Service ............627
C. Boit, K. Scholtens, R. Weiland, S. Görlich, D. Schlenker

Failure Analysis Terms and Definitions .............................................................................635
Ryan Ong

Author Index ........................................................................................................................651

Subject Index .......................................................................................................................653
ix
The Failure Analysis Process
M. Steven Ferrier
Metatech Corporation (cid:3) 1190 SW Sunset Drive (cid:3) Corvallis, OR 97333
Telephone [phone] (cid:3) Email [e-mail]

Introduction. How does an experienced Failure eral analysis formalization intended to make the fail-
Analysis engineer crack a tough analysis? What ure analysis design efficient, rigorous and consistent
makes the difference between a new engineer's Fail- from analysis to analysis and from failure to failure.
ure Analysis approach and the seasoned, effective The formalization amounts to a practical form of sci-
analysis method of a veteran? Can our industry cap- entific method4,5, customized for the failure analysis
ture a formulation of correct Failure Analysis meth- discipline, and enabling faster analysis to satisfy
odology to accelerate the development of new engi- business constraints.
neers and aid the strong skills of experienced ana- The analysis design methodology, or decision en-
lysts? gine, can be formulated as six steps arranged in a cy-
More crucial, perhaps, is the underlying question, cle or loop, shown in Fig. 1. This may not look like a
Are we able as analysts to think abstractly about the Failure Analysis process flow, which is appropriate,
nature of our work? Or are we instead bound to a since it is not, strictly speaking, such a flow. Instead,
tool-focused, concrete way of thinking that has all the these steps in this order form a metaprocess, that is, a
adaptability of the construction material of the same process whose function is to create another process.
name? While our historical inability in the FA indus- Applied to semiconductor failure analysis, this gen-
try to abstract a general process from our daily work eral decision engine metaprocess creates a specific
will probably not doom our discipline, this shortcom- analysis flow for a specific failure based on the facts
ing will certainly rob us of a great deal of efficiency, about the failure, the results of analysis operations,
flexibility and basic understanding of what we do in the body of knowledge about physical causes and
electronic device Failure Analysis. This author has their effects and, finally, inferential logic. This
the conviction that we are a better group of people metaprocess is intended to work properly—that is,
than to allow this shortcoming to continue undetected generate a correct unique failure analysis flow—for
and uncorrected for much longer. any failure analysis of a manufactured product com-
While many or most Failure Analysis departments ing from any of the semiconductor wafer and pack-
make the definition and application of specific analy- aging processes predominant today. Using the ap-
sis process flows a significant priority, the subject of proach described in this tutorial, the analyst of any
general FA methodology remains a minor one in the experience level should become able to make analy-
literature as of this writing.1-3 By way of a summary sis choices in ways that reflect mature failure analysis
remediation, this tutorial paper presents a fully-gen- skills. This approach can thus accelerate the maturity
(end of prior
loop)
Construct an existence-correlation-causation ques-
E/C/C Question
tion (E/C/C Question)

Make a measurement to address that question
(Measurement) Measurement

Interpret the results of the measurement to answer
the E/C/C Question (Interpretation) Interpretation

Cast the answer in an existence-correlation-
causation form (E/C/C Answer)
E/C/C Answer

Build a correlation list of possible prior causes and
their effects (Correlation List)
Correlation List

Select one or more items from the List about which
to construct a new E/C/C Question (Selection)
Selection
(start of next
loop)
Figure 1 Scientific Method Metaprocess Loop for Failure Analysis (unfolded version)
1
of beginning analysts once they have the small also provided the formal structure that, at the conclu-
amount of experience needed to use the metaprocess sion of the analysis, permitted a one-sheet summary
effectively. Some benefits of this methodology will of the failure's cause-effect relationships and the
be described in detail a little later in the tutorial. All analysis flow leading to discovery of the anomaly.
examples of any kind in this tutorial, with one major As with every application of this metaprocess, the
exception described shortly, are hypothetical but pos- resulting analysis flow simply represented an effec-
sible. tive version of good failure analysis. The formal and
The Metaprocess in a Nutshell. Very briefly, flexible codification of the analysis decision-making
here is how this metaprocess produces a correct de- process, however, provided several specific benefits,
vice analysis flow. All analysis starts with under- not least of which was the ability to proceed with
standing the failure mode. We have a part and a high confidence that the problem could and would be
complaint; does the failure mode exist on this part solved. This tutorial describes the application of the
and match the complaint? We make a measurement metaprocess, and also the key measurements and
to confirm the failure mode. If we do confirm the cause-effect relationships in the analysis.
mode, it makes sense, rather than just jumping into a Manufacturing and Failure Mode. The yield
measurement, to ask ourselves what could cause the failure mode, labeled V Leakage, occurred in a
DD
mode. Even if we have no data yet, we can still come specific printhead IC manufactured in a 1.0 um sin-
up with a list of possible causes that may be substan- gle-poly three-metal CMOS process. Although this is
tial. The next step is to write down on our list other a relatively simple wafer process, the mode's charac-
effects of the causes we just wrote down on our list. teristics conspired to counteract any real benefit from
We then select one effect on our list and ask whether the process simplicity. Up to 80% of the IC's manu-
it exists. factured exhibited a slightly elevated (but definitely
The reader will notice that at this point we are anomalous) supply leakage current in a standby con-
back where we started: asking whether an effect ex-
ists. We began by asking whether the effect called
the failure mode exists, and ended by asking whether
an effect on our list existed. This makes it clear that
the pro??cess we are using represents a loop. If we
follow this loop, it will lead us from the failure mode
to the root anomaly. Pursuing a rigorous version of
this approach provides the correct analysis flow.
The Metaprocess in Real Life. To show this,
we start with a real-life example of the use of this ap-
proach, drawn verbatim (excepting a few editorial
excisions) from a published ISTFA paper6. After this
practical example, we will provide some clear defini-
tions of basic terms and then proceed to explain the
six steps on their own merits.
Application of a formal Failure Analysis meta- Figure 2 Cumulative distribution of failing design
leakage behavior of wafer lots with only 20% of I
process to a stubborn yield loss problem provided a DD
currents falling below 200nA.
framework that ultimately facilitated a solution. Ab-
sence of results from conventional failure analysis
techniques such as PEM (Photon Emission Mi-
croscopy) and liquid crystal microthermography frus-
trated early attempts to analyze this low-level supply
leakage failure mode. Subsequently, a reorganized
analysis team attacked the problem using a specific
top-level metaprocessa,4.
Using the metaprocess, analysts generated a spe-
cific unique step-by-step analysis process in real
time. Along the way, this approach encouraged the
creative identification of secondary failure effects
that provided repeated breakthroughs in the analysis
flow. Analysis proceeded steadily toward the failure
cause in spite of its character as a three-way interac-
tion among factors in the IC design, mask generation,
and wafer manufacturing processes. The metaprocess

a A metaprocess is a general process whose pur- Figure 3 Cumulative distribution of leakage behavior
pose and function is to create a specific process to of related but non-failing design with IDD of over 90%
suit specific conditions and requirements. of devices falling below 200nA.
2