Media Computer System for the Altera DE2 Board: Manual

44 Pages·2011·0.435 MB·English

by  Altera Corporation

Media Computer System
for the Altera DE2 Board
ForQuartusII11.0
1 Introduction
ThisdocumentdescribesacomputersystemthatcanbeimplementedontheAlteraDE2developmentandeducation
board. Thissystem,calledtheDE2MediaComputer,isintendedtobeusedforexperimentsincomputerorganization
andembeddedsystems. Tosupporttheseexperiments,thesystemcontainsaprocessor,memory,videodevices,and
somesimpleI/Operipherals. TheFPGAprogrammingfilethatimplementsthissystem,aswellasitsdesignsource
files,canbeobtainedfromtheUniversityProgramsectionofAltera’swebsite.
2 DE2 Media Computer Contents
AblockdiagramoftheDE2MediaComputerisshowninFigure1. ItsmaincomponentsincludetheAlteraNiosII
processor,memoryforprogramanddatastorage,anaudio-in/outport,avideo-outportwithbothpixelandcharacter
buffers,aPS/2serialport,a16×2characterdisplay,parallelportsconnectedtoswitchesandlights,atimermodule,
and an RS 232 serial port. As shown in the figure, the processor and its interfaces to I/O devices are implemented
(cid:176)
insidetheCycloneRIIFPGAchipontheDE2board. AnumberofthecomponentsshowninFigure1aredescribed
intheremainderofthissection,andtheothersarepresentedinsection4.
2.1 NiosIIProcessor
(cid:176)
The Altera NiosRII processor is a 32-bit CPU that can be instantiated in an Altera FPGA chip. Three versions of
theNiosIIprocessorareavailable,designatedeconomy(/e),standard(/s),andfast(/f). TheDE2MediaComputer
includestheNiosII/sversion,whichhasanappropriatefeaturesetforuseinintroductoryexperiments. TheNiosII
processorisconfiguredtoincludefloating-pointhardwaresupport,whichisdescribedinsection4.6.
An overview of the Nios II processor can be found in the document Introduction to the Altera Nios II Processor,
whichis providedin theUniversityProgram’s website. An easywayto beginworking withtheDE2 MediaCom-
puterandtheNiosIIprocessoristomakeuseofautilitycalledtheAlteraMonitorProgram. Thisutilityprovidesan
easywaytoassembleandcompileNiosIIprogramsthatarewrittenineitherassemblylanguageortheCprogram-
minglanguage. TheMonitorProgram,whichcanbedownloadedfromAltera’swebsite,isanapplicationprogram
that runs on the host computer connected to the DE2 board. The Monitor Program can be used to control the exe-
cutionofcodeonNiosII,list(andedit)thecontentsofprocessorregisters,display/editthecontentsofmemoryon
the DE2 board, and similar operations. The Monitor Program includes the DE2 Media Computer as a predesigned
systemthatcanbedownloadedontotheDE2board,aswellasseveralsampleprogramsinassemblylanguageandC
thatshowhowtousetheDE2MediaComputer’speripherals. SomeimagesthatshowhowtheDE2MediaComputer
isintegratedwiththeMonitorProgramaredescribedinsection8. AnoverviewoftheMonitorProgramisavailable
inthedocumentAlteraMonitorProgramTutorial,whichisprovidedintheUniversityProgramwebsite.
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Host computer
(USB connection)
DE2 Board
USB
Blaster KEY Audio VGA RS-232
0
CODEC DAC chip
Reset
JTAG port Nios II processor
Audio A/V Video-out Serial PS/2
port config port port port
System Interval Floating Cyclone II On-chip
ID timer point FPGA chip memory
Parallel Parallel Parallel LCD Parallel SRAM SDRAM Parallel
port ports ports port port controller controller ports
16 x 2 SRAM SDRAM
Switches LEDR 7-Segment KEY Expansion
17-0 3-1
chip chip
SW LEDG HEX7-HEX0 JP0, JP1
17-0 8-0
Figure1. BlockdiagramoftheDE2MediaComputer.
AsindicatedinFigure1,theNiosIIprocessorcanberesetbypressingKEY ontheDE2board. Theresetmechanism
0
is discussed further in section 3. All of the I/O peripherals in the DE2 Media Computer are accessible by the
processorasmemorymappeddevices,usingtheaddressrangesthataregiveninthefollowingsubsections.
2.2 MemoryComponents
The DE2 Media Computer has three types of memory components: SDRAM, SRAM, and on-chip memory inside
theFPGAchip. Eachtypeofmemoryisdescribedbelow.
2.2.1 SDRAM
An SDRAM Controller provides a 32-bit interface to the synchronous dynamic RAM (SDRAM) chip on the DE2
board, which is organized as 1M x 16 bits x 4 banks. It is accessible by the Nios II processor using word (32-bit),
halfword(16-bit),orbyteoperations,andismappedtotheaddressspace0x00000000to0x007FFFFF.
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2.2.2 SRAM
An SRAM Controller provides a 32-bit interface to the static RAM (SRAM) chip on the DE2 board. This SRAM
chipisorganizedas256Kx16bits,butisaccessiblebytheNiosIIprocessorusingword(32-bit),halfword(16-bit),
orbyteoperations. TheSRAMmemoryismappedtotheaddressspace0x08000000to0x0807FFFF.
2.2.3 On-ChipMemory
The DE2 Media Computer includes a 8-Kbyte memory that is implemented in the Cyclone II FPGA chip. This
memoryisorganizedas8Kx8bits,andspansaddressesintherange0x09000000to0x09001FFF.Thismemory
isusedasacharacterbufferforthevideo-outport,whichisdescribedinsection4.2.
2.3 ParallelPorts
The DE2 Media Computer includes several parallel ports that support input, output, and bidirectional transfers of
data between the Nios II processor and I/O peripherals. As illustrated in Figure 2, each parallel port is assigned
a Base address and contains up to four 32-bit registers. Ports that have output capability include a writable Data
register, and ports with input capability have a readable Data register. Bidirectional parallel ports also include a
Direction register that has the same bit-width as the Data register. Each bit in the Data register can be configured
asaninputbysettingthecorrespondingbitintheDirectionregisterto0,orasanoutputbysettingthisbitposition
to1. TheDirectionregisterisassignedtheaddressBase+4.
Address 31 30 . . . 4 3 2 1 0
Base Input or output data bits Data register
Base + 4 DDiirreeccttiioonn bbiittss Direction register
Base + 8 Mask bits Interruptmask register
Base + C Edge bits Edgecapture register
Figure2. ParallelportregistersintheDE2MediaComputer.
Some of the parallel ports in the DE2 Media Computer have registers at addresses Base + 8 and Base + C, as
indicatedinFigure2. Theseregistersarediscussedinsection3.
2.3.1 RedandGreenLEDParallelPorts
The red lights LEDR17−0 and green lights LEDG8−0 on the DE2 board are each driven by an output parallel port,
as illustrated in Figure 3. The port connected to LEDR contains an 18-bit write-only Data register, which has the
address 0x10000000. The port for LEDG has a nine-bit Data register that is mapped to address 0x10000010.
Thesetworegisterscanbewrittenusingwordaccesses,andtheupperbitsnotusedintheregistersareignored.
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Address
0x10000000
31 Unused 18 17 . . . 0 Data register
LEDR LEDR
17 0
0x10000010
31 Unused 9 8 . . . 0 Data register
LEDG LEDG
8 0
Figure3. OutputparallelportsforLEDRandLEDG.
2.3.2 7-SegmentDisplaysParallelPort
Therearetwoparallelportsconnectedtothe7-segmentdisplaysontheDE2board,eachofwhichcomprisesa32-bit
write-onlyDataregister. AsindicatedinFigure4,theregisterataddress0x10000020drivesdigitsHEX3toHEX0,
and the register at address 0x10000030 drives digits HEX7 to HEX4. Data can be written into these two registers
by using word operations. This data directly controls the segments of each display, according to the bit locations
giveninFigure4. Thelocationsofsegments6to0ineachseven-segmentdisplayontheDE2boardisillustratedon
therightsideofthefigure.
Address
0x10000020
31 30 24 23 22 16 15 14 8 7 6 0 Data register 0
... ... ... ... 5 1
6
4 2
HEX3 HEX2 HEX1 HEX0
6-0 6-0 6-0 6-0
3
Segments
0x10000030
Data register
31 30 24 23 22 16 15 14 8 7 6 0
... ... ... ...
HEX7 HEX6 HEX5 HEX4
6-0 6-0 6-0 6-0
Figure4. Bitlocationsforthe7-segmentdisplaysparallelports.
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2.3.3 SliderSwitchParallelPort
TheSW17−0 sliderswitchesontheDE2boardareconnectedtoaninputparallelport. AsillustratedinFigure5,this
portcomprisesan18-bitread-onlyDataregister,whichismappedtoaddress0x10000040.
Address
0x10000040
31 Unused 18 17 . . . 0 Data register
. . .
SW SW
17 0
Figure5. Dataregisterinthesliderswitchparallelport.
2.3.4 PushbuttonParallelPort
The parallel port connected to the KEY3−1 pushbutton switches on the DE2 board comprises three 3-bit registers,
as shown in Figure 6. These registers have the base addresses 0x10000050 to 0x1000005C and can be accessed
usingwordoperations. Theread-onlyDataregisterprovidesthevaluesoftheswitchesKEY ,KEY andKEY . Bit
3 2 1
0 of the Data register is not used, because, as discussed in section 2.1, the corresponding switch KEY is reserved
0
foruseasaresetmechanismfortheDE2MediaComputer. TheothertworegistersshowninFigure6,ataddresses
0x10000058and0x1000005C,arediscussedinsection3.
Address 31 30 . . . 4 3 2 1 0
0x10000050 Unused KEY Data register
3-1
Unused Unused
0x10000058 Unused Mask bits Interruptmask register
0x1000005C Unused Edge bits Edgecapture register
Figure6. Registersusedinthepushbuttonparallelport.
2.3.5 ExpansionParallelPorts
TheDE2MediaComputerincludestwobidirectionalparallelportsthatareconnectedtotheJP1andJP2expansion
headers on the DE2board. Each of these parallelports includes the four 32-bit registers thatwere described previ-
ouslyforFigure2. ThebaseaddressesoftheportsconnectedtoJP1andJP2are0x10000060and0x10000070,
respectively. Figure7givesadiagramoftheJP1andJP2expansionconnectorsontheDE2board,andshowshow
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therespectiveparallelportDataregisterbits,D31−0,areassignedtothepinsontheconnector. Thefigureshowsthat
bit D of the parallel port for JP1 is assigned to the pin at the top right corner of the connector, bit D is assigned
0 1
belowthis,andsoon. NotethatsomeofthepinsonJP1andJP2arenotusableasinput/outputconnections,andare
thereforenotusedbytheparallelports. Also,only32ofthe36datapinsthatappearoneachconnectorcanbeused.
JP1 JP2
Pin 1 D Pin 1 D
0 0
D D
1 1
D D D D
2 3 2 3
D D D D
4 5 4 5
D D D D
6 7 6 7
Unused Unused
D D D D
8 9 8 9
D D D D
10 11 10 11
D D D D
12 13 12 13
D D
14 14
D D
15 15
D D D D
16 17 16 17
D D D D
18 19 18 19
D D D D
20 21 20 21
Unused Unused
D D D D
22 23 22 23
D D D D
24 25 24 25
D D D D
26 27 26 27
D D D D
28 29 28 29
D D Pin 40 D D Pin 40
30 31 30 31
Figure7. AssignmentofparallelportbitstopinsonJP1andJP2.
2.3.6 UsingtheParallelPortswithAssemblyLanguageCodeandCCode
TheDE2MediaComputerprovidesaconvenientplatformforexperimentingwithNiosIIassemblylanguagecode,
or C code. A simple example of such code is provided in Figures 8 and 9. Both programs perform the same
operations,andillustratetheuseofparallelportsbyusingeitherassemblylanguageorCcode.
The code in the figures displays the values of the SW switches on the red LEDs, and the pushbutton keys on the
green LEDs. It also displays a rotating pattern on 7-segment displays HEX3 ... HEX0 and HEX7 ... HEX4. This
patternisshiftedtotherightbyusingaNiosIIrotateinstruction,andadelayloopisusedtomaketheshiftingslow
enough to observe. The pattern on the HEX displays can be changed to the values of the SW switches by pressing
anyofpushbuttonsKEY ,KEY ,orKEY (recallfromsection2.1thatKEY causesaresetoftheNiosIIprocessor).
3 2 1 0
Whenapushbuttonkeyispressed,theprogramwaitsinaloopuntilthekeyisreleased.
ThesourcecodefilesshowninFigures8and9aredistributedaspartoftheAlteraMonitorProgram. Thefilescan
befoundundertheheadingsampleprograms,andareidentifiedbythenameGettingStarted.
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/********************************************************************************
*ThisprogramdemonstratestheuseofparallelportsintheDE2MediaComputer:
* 1. displaystheSWswitchvaluesontheredLEDR
* 2. displaystheKEY[3..1]pushbuttonvaluesonthegreenLEDG
* 3. displaysarotatingpatternontheHEXdisplays
* 4. ifKEY[3..1]ispressed,usestheSWswitchesasthepattern
********************************************************************************/
.text /*executablecodefollows*/
.global_start
_start:
/*initializebaseaddressesofparallelports*/
movia r15,0x10000040 /*SWsliderswitchbaseaddress*/
movia r16,0x10000000 /*redLEDbaseaddress*/
movia r17,0x10000050 /*pushbuttonKEYbaseaddress*/
movia r18,0x10000010 /*greenLEDbaseaddress*/
movia r20,0x10000020 /*HEX3_HEX0baseaddress*/
movia r21,0x10000030 /*HEX7_HEX4baseaddress*/
movia r19,HEX_bits
ldwio r6,0(r19) /*loadpatternforHEXdisplays*/
DO_DISPLAY:
ldwio r4,0(r15) /*loadinputfromsliderswitches*/
stwio r4,0(r16) /*writetoredLEDs*/
ldwio r5,0(r17) /*loadinputfrompushbuttons*/
stwio r5,0(r18) /*writetogreenLEDs*/
beq r5,r0,NO_BUTTON
mov r6,r4 /*copySWswitchvaluesontoHEXdisplays*/
WAIT:
ldwio r5,0(r17) /*loadinputfrompushbuttons*/
bne r5,r0,WAIT /*waitforbuttonrelease*/
NO_BUTTON:
stwio r6,0(r20) /*storetoHEX3... HEX0*/
stwio r6,0(r21) /*storetoHEX7... HEX4*/
roli r6,r6,1 /*rotatethedisplayedpattern*/
movia r7,500000 /*delaycounter*/
DELAY:
subi r7,r7,1
bne r7,r0,DELAY
br DO_DISPLAY
.data /*datafollows*/
HEX_bits:
.word0x0000000F
.end
Figure8. AnexampleofNiosIIassemblylanguagecodethatusesparallelports.
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/********************************************************************************
*ThisprogramdemonstratestheuseofparallelportsintheDE2MediaComputer:
* 1. displaystheSWswitchvaluesontheredLEDR
* 2. displaystheKEY[3..1]pushbuttonvaluesonthegreenLEDG
* 3. displaysarotatingpatternontheHEXdisplays
* 4. ifKEY[3..1]ispressed,usestheSWswitchesasthepattern
********************************************************************************/
intmain(void)
{
/*DeclarevolatilepointerstoI/Oregisters(volatilemeansthatIOloadandstore
instructions(e.g.,ldwio,stwio)willbeusedtoaccessthesepointerlocations)*/
volatileint*red_LED_ptr =(int*)0x10000000; //redLEDaddress
volatileint*green_LED_ptr =(int*)0x10000010; //greenLEDaddress
volatileint*HEX3_HEX0_ptr =(int*)0x10000020; //HEX3_HEX0address
volatileint*HEX7_HEX4_ptr =(int*)0x10000030; //HEX7_HEX4address
volatileint*SW_switch_ptr =(int*)0x10000040; //SWsliderswitchaddress
volatileint*KEY_ptr =(int*)0x10000050; //pushbuttonKEYaddress
intHEX_bits=0x0000000F; //patternforHEXdisplays
intSW_value,KEY_value,delay_count;
while(1)
{
SW_value=*(SW_switch_ptr); //readtheSWsliderswitchvalues
*(red_LED_ptr)=SW_value; //lightuptheredLEDs
KEY_value=*(KEY_ptr); //readthepushbuttonKEYvalues
*(green_LED_ptr)=KEY_value; //lightupthegreenLEDs
if(KEY_value!=0) //checkifanyKEYwaspressed
{
HEX_bits=SW_value; //setpatternusingSWvalues
while(*KEY_ptr); //waitforpushbuttonKEYrelease
}
*(HEX3_HEX0_ptr)=HEX_bits; //displaypatternonHEX3... HEX0
*(HEX7_HEX4_ptr)=HEX_bits; //displaypatternonHEX7... HEX4
if(HEX_bits&0x80000000) /*rotatethepatternshownontheHEXdisplays*/
HEX_bits=(HEX_bits<<1)|1;
else
HEX_bits=HEX_bits<<1;
for(delay_count=500000;delay_count!=0;−−delay_count);//delayloop
}//endwhile
}
Figure9. AnexampleofCcodethatusesparallelports.
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2.4 JTAGPort
The JTAG port implements a communication link between the DE2 board and its host computer. This link is
automatically used by the Quartus II software to transfer FPGA programming files into the DE2 board, and by
the Altera Monitor Program. The JTAG port also includes a UART, which can be used to transfer character data
betweenthehostcomputerandprogramsthatareexecutingontheNiosIIprocessor. IftheAlteraMonitorProgram
isusedonthehostcomputer,thenthischaracterdataissentandreceivedthroughitsTerminalWindow. TheNiosII
programming interface of the JTAG UART consists of two 32-bit registers, as shown in Figure 10. The register
mapped to address 0x10001000 is called the Data register and the register mapped to address 0x10001004 is
calledtheControlregister.
Address 31 . . . 16 15 14. . .11 10 9 8 7 . . . 1 0
0x10001000 RAVAIL RVALID Unused DATA Data register
0x10001004 WSPACE Unused AC WI RI WE RE Control register
Figure10. JTAGUARTregisters.
When character data from the host computer is received by the JTAG UART it is stored in a 64-character FIFO.
ThenumberofcharacterscurrentlystoredinthisFIFOisindicatedinthefieldRAVAIL,whicharebits31−16ofthe
Dataregister. IfthereceiveFIFOoverflows, thenadditionaldataislost. WhendataispresentinthereceiveFIFO,
then the value of RAVAIL will be greater than 0 and the value of bit 15, RVALID, will be 1. Reading the character
at the head of the FIFO, which is provided in bits 7−0, decrements the value of RAVAIL by one and returns this
decremented value as part of the read operation. If no data is present in the receive FIFO, then RVALID will be set
to0andthedatainbits7−0isundefined.
TheJTAGUARTalsoincludesa64-characterFIFOthatstoresdatawaitingtobetransmittedtothehostcomputer.
Character data is loaded into this FIFO by performing a write to bits 7−0 of the Data register in Figure 10. Note
that writing into this register has no effect on received data. The amount of space, WSPACE, currently available in
thetransmitFIFOisprovidedinbits31−16oftheControlregister. IfthetransmitFIFOisfull,thenanycharacters
writtentotheDataregisterwillbelost.
Bit10intheControlregister,calledAC,hasthevalue1iftheJTAGUARThasbeenaccessedbythehostcomputer.
Thisbitcanbeusedtocheckifaworkingconnectiontothehostcomputerhasbeenestablished. TheACbitcanbe
clearedto0bywritinga1intoit.
TheControlregisterbitsRE,WE,RI,andWIaredescribedinsection3.
2.4.1 UsingtheJTAGUARTwithAssemblyLanguageCodeandCCode
Figures 11 and 12 give simple examples of assembly language and C code, respectively, that use the JTAG UART.
Bothversionsofthecodeperformthesamefunction,whichistofirstsendanASCIIstringtotheJTAGUART,and
then enter an endless loop. In the loop, the code reads character data that has been received by the JTAG UART,
and echoes this data back to the UART for transmission. If the program is executed by using the Altera Monitor
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Program,thenanykeyboardcharacterthatistypedintotheTerminalWindowoftheMonitorProgramwillbeechoed
back,causingthecharactertoappearintheTerminalWindow.
The source code files shown in Figures 11 and 12 are made available as part of the Altera Monitor Program. The
filescanbefoundundertheheadingsampleprograms,andareidentifiedbythenameJTAGUART.
/********************************************************************************
*ThisprogramdemonstratesuseoftheJTAGUARTportintheDE2MediaComputer
*
*Itperformsthefollowing:
* 1. sendsatextstringtotheJTAGUART
* 2. readscharacterdatafromtheJTAGUART
* 3. echosthecharacterdatabacktotheJTAGUART
********************************************************************************/
.text /*executablecodefollows*/
.global _start
_start:
/*setupstackpointer*/
movia sp,0x007FFFFC /*stackstartsfromhighestmemoryaddressinSDRAM*/
movia r6,0x10001000 /*JTAGUARTbaseaddress*/
/*printatextstring*/
movia r8,TEXT_STRING
LOOP:
ldb r5,0(r8)
beq r5,zero,GET_JTAG /*stringisnull-terminated*/
call PUT_JTAG
addi r8,r8,1
br LOOP
/*readandechocharacters*/
GET_JTAG:
ldwio r4,0(r6) /*readtheJTAGUARTDataregister*/
andi r8,r4,0x8000 /*checkifthereisnewdata*/
beq r8,r0,GET_JTAG /*ifnodata,wait*/
andi r5,r4,0x00ff /*thedataisintheleastsignificantbyte*/
call PUT_JTAG /*echocharacter*/
br GET_JTAG
.end
Figure11. AnexampleofassemblylanguagecodethatusestheJTAGUART(Parta).
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