Table Of ContentHDL Coder™
Getting Started Guide
R2016a
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HDL Coder™ Getting Started Guide
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Revision History
March 2012 Online only New for Version 3.0 (Release 2012a)
September 2012 Online only Revised for Version 3.1 (Release 2012b)
March 2013 Online only Revised for Version 3.2 (Release 2013a)
September 2013 Online only Revised for Version 3.3 (Release 2013b)
March 2014 Online only Revised for Version 3.4 (Release 2014a)
October 2014 Online only Revised for Version 3.5 (Release 2014b)
March 2015 Online only Revised for Version 3.6 (Release 2015a)
September 2015 Online only Revised for Version 3.7 (Release 2015b)
October 2015 Online only Rereleased for Version 3.6.1 (Release
2015aSP1)
March 2016 Online only Revised for Version 3.8 (Release 2016a)
Contents
About HDL Coder
1
HDL Coder Product Description . . . . . . . . . . . . . . . . . . . . . . . 1-2
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Supported Third-Party Tools and Hardware . . . . . . . . . . . . . 1-3
Third-Party Synthesis Tools and Version Support . . . . . . . . . 1-3
FPGA-in-the-Loop Hardware . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Simulink Real-Time FPGA I/O Hardware . . . . . . . . . . . . . . . 1-4
FPGA Turnkey Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
VHDL and Verilog Language Support . . . . . . . . . . . . . . . . . . 1-6
HDL Coder Supported Hardware . . . . . . . . . . . . . . . . . . . . . . 1-7
Getting Started with HDL Coder
2
Tool Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Synthesis Tool Path Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
HDL Simulator Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Xilinx System Generator Setup for ModelSim Simulation . . . 2-4
Altera DSP Builder Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
FPGA Simulation Library Setup . . . . . . . . . . . . . . . . . . . . . . 2-5
C/C++ Compiler Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Prepare Simulink Model For HDL Code Generation . . . . . . 2-6
Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
HDL Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
HDL Cosimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
v
FPGA-in-the-Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Tutorials
3
HDL Code Generation from a MATLAB Algorithm . . . . . . . . 3-2
About the Algorithm in This Example . . . . . . . . . . . . . . . . . . 3-2
Copying Files Locally . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Checking Your Synthesis Tool Setup . . . . . . . . . . . . . . . . . . . 3-4
Testing the Original MATLAB Algorithm . . . . . . . . . . . . . . . 3-4
Setting Up an HDL Coder Project . . . . . . . . . . . . . . . . . . . . . 3-5
Creating Fixed-Point Versions of the Algorithm and Test
Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Generating HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
HDL Code Generation from a Simulink Model . . . . . . . . . . 3-15
Before You Generate Code . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Overview of Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
The sfir_fixed Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Generate Code Using the HDL Workflow Advisor . . . . . . . . 3-19
Generate HDL Code Using the Command Line . . . . . . . . . . 3-22
Generate HDL Code Using the Configuration Parameters
Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Simulating and Verifying Generated HDL Code . . . . . . . . . 3-39
vi Contents
1
About HDL Coder
• “HDL Coder Product Description” on page 1-2
• “Supported Third-Party Tools and Hardware” on page 1-3
• “VHDL and Verilog Language Support” on page 1-6
• “HDL Coder Supported Hardware” on page 1-7
1
About HDL Coder
HDL Coder Product Description
Generate VHDL and Verilog code for FPGA and ASIC designs
HDL Coder™ generates portable, synthesizable VHDL® and Verilog® code from
MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code
can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx® and
Altera® FPGAs. You can control HDL architecture and implementation, highlight critical
paths, and generate hardware resource utilization estimates. HDL Coder provides
traceability between your Simulink model and the generated Verilog and VHDL code,
enabling code verification for high-integrity applications adhering to DO-254 and other
standards.
Key Features
• Target-independent, synthesizable VHDL and Verilog code
• Code generation support for MATLAB functions, System objects and Simulink blocks
• Mealy and Moore finite-state machines and control logic implementations using
Stateflow
• Workflow advisor for programming Xilinx and Altera application boards
• Resource sharing and retiming for area-speed tradeoffs
• Code-to-model and model-to-code traceability for DO-254
• Legacy code integration
1-2
Supported Third-Party Tools and Hardware
Supported Third-Party Tools and Hardware
In this section...
“Third-Party Synthesis Tools and Version Support” on page 1-3
“FPGA-in-the-Loop Hardware” on page 1-3
“Simulink Real-Time FPGA I/O Hardware” on page 1-4
“FPGA Turnkey Hardware” on page 1-4
Third-Party Synthesis Tools and Version Support
The HDL Workflow Advisor is tested with the following third-party FPGA synthesis
tools:
• Altera Quartus II 15.0
• Xilinx Vivado® Design Suite 2015.2
• Xilinx ISE 14.7
• Xilinx ISE 10.1 is supported only for compatibility with Speedgoat FPGA target
devices.
Speedgoat IO301, IO303, and IO311 FPGA IO boards, which use Xilinx Virtex-
II FPGAs, are tested with Xilinx ISE version 10.1. Before you select one of these
Speedgoat devices in the HDL Workflow Advisor, make sure that you have installed
Xilinx ISE 10.1. See “Generate Simulink Real-Time Interface for Speedgoat Boards”
for more information.
To use third-party synthesis tools with HDL Coder, a supported synthesis tool must be
installed, and the synthesis tool executable must be on the system path. For details, see
“Tool Setup” on page 2-2.
FPGA-in-the-Loop Hardware
The FPGAs supported for FPGA-in-the-loop simulation with HDL Verifier™ are listed in
the HDL Verifier documentation.
You can also add custom FPGA boards using the FPGA Board Manager. See “FPGA
Board Customization” for details.
1-3
1
About HDL Coder
For FPGA-in-the-Loop or Customization for USRP® Device using the HDL Workflow
Advisor, a supported synthesis tool must be installed, and the synthesis tool executable
must be on the system path. For details, see “Tool Setup” on page 2-2.
Simulink Real-Time FPGA I/O Hardware
The FPGA I/O boards supported for use with the Simulink Real-Time™ FPGA IO
workflow are listed in the Simulink Real-Time documentation.
FPGA Turnkey Hardware
The following hardware is supported for the FPGA Turnkey workflow:
• Altera Arria® II GX FPGA development kit
• Altera Cyclone® III FPGA development kit
• Altera Cyclone IV GX FPGA development kit
• Altera DE2–115 development and education board
• XUP Atlys Spartan-6 development board
• Xilinx Spartan-3A DSP 1800A development board
• Xilinx Spartan-6 SP605 development board
• Xilinx Virtex-4 ML401 development board
• Xilinx Virtex-4 ML402 development board
• Xilinx Virtex-5 ML506 development board
• Xilinx Virtex-6 ML605 development board
For FPGA development boards that have more than one FPGA device, only one such
device can be used with FPGA Turnkey.
Supported FPGA Device Families for Board Customization
You can also add custom FPGA boards using the FPGA Board Manager. HDL Coder
supports the following FPGA device families for board customization; that is, when you
create your own board definition file. See “FPGA Board Customization”.
Device Family
Xilinx Kintex7
1-4
