Matlab Filter Design HDL Coder documentation

438 Pages·2016·3.195 MB·English

Filter Design HDL Coder™
User's Guide
R2016a
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Filter Design HDL Coder™ User's Guide
© COPYRIGHT 2004–2016 by The MathWorks, Inc.
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Revision History
June 2004 Online only New for Version 1.0 (Release 14)
October 2004 Online only Revised for Version 1.1 (Release 14SP1)
March 2005 Online only Revised for Version 1.2 (Release 14SP2)
September 2005 Online only Revised for Version 1.3 (Release 14SP3)
March 2006 Online only Revised for Version 1.4 (Release 2006a)
September 2006 Online only Revised for Version 1.5 (Release 2006b)
March 2007 Online only Revised for Version 2.0 (Release 2007a)
September 2007 Online only Revised for Version 2.1 (Release 2007b)
March 2008 Online only Revised for Version 2.2 (Release 2008a)
October 2008 Online only Revised for Version 2.3 (Release 2008b)
March 2009 Online only Revised for Version 2.4 (Release 2009a)
September 2009 Online only Revised for Version 2.5 (Release 2009b)
March 2010 Online only Revised for Version 2.6 (Release 2010a)
September 2010 Online only Revised for Version 2.7 (Release 2010b)
April 2011 Online only Revised for Version 2.8 (Release 2011a)
September 2011 Online only Revised for Version 2.9 (Release 2011b)
March 2012 Online only Revised for Version 2.9.1 (Release 2012a)
September 2012 Online only Revised for Version 2.9.2 (Release 2012b)
March 2013 Online only Revised for Version 2.9.3 (Release 2013a)
September 2013 Online only Revised for Version 2.9.4 (Release 2013b)
March 2014 Online only Revised for Version 2.9.5 (Release 2014a)
October 2014 Online only Revised for Version 2.9.6 (Release 2014b)
March 2015 Online only Revised for Version 2.9.7 (Release 2015a)
September 2015 Online only Revised for Version 2.10 (Release 2015b)
March 2016 Online only Revised for Version 3.0 (Release 2016a)

Contents
Getting Started
1
Filter Design HDL Coder Product Description . . . . . . . . . . . 1-2
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Automated HDL Code Generation . . . . . . . . . . . . . . . . . . . . . . 1-3
Basic FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Create a Folder for Your Tutorial Files . . . . . . . . . . . . . . . . . 1-4
Design a FIR Filter in FDATool . . . . . . . . . . . . . . . . . . . . . . 1-4
Quantize the Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Configure and Generate VHDL Code . . . . . . . . . . . . . . . . . . 1-9
Explore the Generated VHDL Code . . . . . . . . . . . . . . . . . . . 1-16
Verify the Generated VHDL Code . . . . . . . . . . . . . . . . . . . . 1-17
Optimized FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Create a Folder for Your Tutorial Files . . . . . . . . . . . . . . . . 1-24
Design the FIR Filter in FDATool . . . . . . . . . . . . . . . . . . . . 1-24
Quantize the FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Configure and Generate Optimized Verilog Code . . . . . . . . . 1-29
Explore the Optimized Generated Verilog Code . . . . . . . . . . 1-38
Verify the Generated Verilog Code . . . . . . . . . . . . . . . . . . . 1-39
IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Create a Folder for Your Tutorial Files . . . . . . . . . . . . . . . . 1-45
Design an IIR Filter in FDATool . . . . . . . . . . . . . . . . . . . . . 1-45
Quantize the IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47
Configure and Generate VHDL Code . . . . . . . . . . . . . . . . . 1-51
Explore the Generated VHDL Code . . . . . . . . . . . . . . . . . . . 1-56
Verify the Generated VHDL Code . . . . . . . . . . . . . . . . . . . . 1-58
v
HDL Filter Code Generation Fundamentals
2
Starting Filter Design HDL Coder . . . . . . . . . . . . . . . . . . . . . 2-2
Opening the Filter Design HDL Coder GUI from FDATool . . 2-2
Opening the Filter Design HDL Coder GUI from the
filterbuilder GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Opening the Filter Design HDL Coder GUI Using the
fdhdltool Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Selecting Target Language . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Generating HDL Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Applying Your Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Generating HDL Code from the GUI . . . . . . . . . . . . . . . . . . 2-14
Generating HDL Code Using generatehdl . . . . . . . . . . . . 2-15
Capturing Code Generation Settings . . . . . . . . . . . . . . . . . . 2-16
Closing Code Generation Session . . . . . . . . . . . . . . . . . . . . . 2-18
HDL Code for Supported Filter Structures
3
Generate HDL from Filter System Objects . . . . . . . . . . . . . . . 3-2
Multirate Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Supported Multirate Filter Types . . . . . . . . . . . . . . . . . . . . . 3-4
Generating Multirate Filter Code . . . . . . . . . . . . . . . . . . . . . 3-4
Code Generation Options for Multirate Filters . . . . . . . . . . . 3-4
Variable Rate CIC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Supported Variable Rate CIC Filter Types . . . . . . . . . . . . . 3-10
Code Generation Options for Variable Rate CIC Filters . . . . 3-10
Cascade Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Supported Cascade Filter Types . . . . . . . . . . . . . . . . . . . . . 3-13
Generating Cascade Filter Code . . . . . . . . . . . . . . . . . . . . . 3-13
Limitations for Code Generation with Cascade Filters . . . . . 3-14
vi Contents
Polyphase Sample Rate Converters . . . . . . . . . . . . . . . . . . . 3-16
Code Generation for Polyphase Sample Rate Converter . . . . 3-16
HDL Implementation for Polyphase Sample Rate Converter 3-16
Multirate Farrow Sample Rate Converters . . . . . . . . . . . . . 3-19
Code Generation for Multirate Farrow Sample Rate
Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Generating Code for dsp.FarrowRateConverter Filters at the
Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Generating Code for dsp.FarrowRateConverter Filters in
the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Single-Rate Farrow Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
About Code Generation for Single-Rate Farrow Filters . . . . 3-23
Code Generation Properties for Farrow Filters . . . . . . . . . . 3-23
GUI Options for Farrow Filters . . . . . . . . . . . . . . . . . . . . . . 3-25
Farrow Filter Code Generation Mechanics . . . . . . . . . . . . . 3-27
Programmable Filter Coefficients for FIR Filters . . . . . . . . 3-30
GUI Options for Programmable Coefficients . . . . . . . . . . . . 3-31
Generating a Test Bench for Programmable FIR Coefficients 3-33
Using Programmable Coefficients with Serial FIR Filter
Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Programmable Filter Coefficients for IIR Filters . . . . . . . . 3-40
Generate a Processor Interface for a Programmable IIR
Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Generating a Test Bench for Programmable IIR Coefficients 3-43
Addressing Scheme for Loading IIR Coefficients . . . . . . . . . 3-45
DUC and DDC System Objects . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Optimization of HDL Filter Code
4
Speed vs. Area Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Overview of Speed or Area Optimizations . . . . . . . . . . . . . . . 4-2
Parallel and Serial Architectures . . . . . . . . . . . . . . . . . . . . . 4-3
vii
Specifying Speed vs. Area Tradeoffs via generatehdl
Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Select Architectures in the Generate HDL Dialog Box . . . . . . 4-9
Distributed Arithmetic for FIR Filters . . . . . . . . . . . . . . . . . 4-21
Distributed Arithmetic Overview . . . . . . . . . . . . . . . . . . . . 4-21
Requirements and Considerations for Generating Distributed
Arithmetic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Distributed Arithmetic via generatehdl Properties . . . . . . . 4-24
Distributed Arithmetic Options in the Generate HDL Dialog
Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Architecture Options for Cascaded Filters . . . . . . . . . . . . . . 4-30
CSD Optimizations for Coefficient Multipliers . . . . . . . . . . 4-31
Improving Filter Performance with Pipelining . . . . . . . . . . 4-32
Optimizing the Clock Rate with Pipeline Registers . . . . . . . 4-32
Multiplier Input and Output Pipelining for FIR Filters . . . . 4-33
Optimizing Final Summation for FIR Filters . . . . . . . . . . . . 4-34
Specifying or Suppressing Registered Input and Output . . . 4-36
Overall HDL Filter Code Optimization . . . . . . . . . . . . . . . . . 4-38
Optimize for HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38
Set Error Margin for Test Bench . . . . . . . . . . . . . . . . . . . . . 4-39
Customization of HDL Filter Code
5
HDL File Names and Locations . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Setting the Location of Generated Files . . . . . . . . . . . . . . . . 5-2
Naming the Generated Files and Filter Entity . . . . . . . . . . . 5-3
Set HDL File Name Extensions . . . . . . . . . . . . . . . . . . . . . . 5-4
Splitting Entity and Architecture Code Into Separate Files . . 5-6
HDL Identifiers and Comments . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Specifying a Header Comment . . . . . . . . . . . . . . . . . . . . . . . 5-8
Resolving Entity or Module Name Conflicts . . . . . . . . . . . . 5-10
Resolving HDL Reserved Word Conflicts . . . . . . . . . . . . . . . 5-11
Setting the Postfix String for VHDL Package Files . . . . . . . 5-14
viii Contents
Specifying a Prefix for Filter Coefficients . . . . . . . . . . . . . . 5-15
Specifying a Postfix String for Process Block Labels . . . . . . 5-16
Setting a Prefix for Component Instance Names . . . . . . . . . 5-17
Setting a Prefix for Vector Names . . . . . . . . . . . . . . . . . . . . 5-18
Ports and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Naming HDL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Specifying the HDL Data Type for Data Ports . . . . . . . . . . . 5-21
Selecting Asynchronous or Synchronous Reset Logic . . . . . . 5-22
Setting the Asserted Level for the Reset Input Signal . . . . . 5-23
Suppressing Generation of Reset Logic . . . . . . . . . . . . . . . . 5-25
HDL Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Representing VHDL Constants with Aggregates . . . . . . . . . 5-27
Unrolling and Removing VHDL Loops . . . . . . . . . . . . . . . . 5-28
Using the VHDL rising_edge Function . . . . . . . . . . . . . . . . 5-29
Suppressing the Generation of VHDL Inline Configurations 5-30
Specifying VHDL Syntax for Concatenated Zeros . . . . . . . . 5-31
Specifying Input Type Treatment for Addition and Subtraction
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Suppressing Verilog Time Scale Directives . . . . . . . . . . . . . 5-33
Using Complex Data and Coefficients . . . . . . . . . . . . . . . . . 5-34
Verification of Generated HDL Filter Code
6
Testing with an HDL Test Bench . . . . . . . . . . . . . . . . . . . . . . 6-2
Workflow for Testing with an HDL Test Bench . . . . . . . . . . . 6-2
Enabling Test Bench Generation . . . . . . . . . . . . . . . . . . . . . . 6-9
Renaming the Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Splitting Test Bench Code and Data into Separate Files . . . 6-13
Configuring the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Configuring Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Setting a Hold Time for Data Input Signals . . . . . . . . . . . . 6-19
Setting an Error Margin for Optimized Filter Code . . . . . . . 6-21
Setting an Initial Value for Test Bench Inputs . . . . . . . . . . 6-23
Setting Test Bench Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Setting a Postfix for Reference Signal Names . . . . . . . . . . . 6-25
ix
Cosimulation of HDL Code with HDL Simulators . . . . . . . . 6-27
Generating HDL Cosimulation Blocks for Use with HDL
Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Generating a Simulink Model for Cosimulation with an HDL
Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Integration with Third-Party EDA Tools . . . . . . . . . . . . . . . 6-36
Generate a Default Script . . . . . . . . . . . . . . . . . . . . . . . . . . 6-36
Customize Scripts for Compilation and Simulation . . . . . . . 6-37
Synthesis and Workflow Automation
7
Automation Scripts for Third-Party Synthesis Tools . . . . . . 7-2
Select a Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Customize Synthesis Script Generation . . . . . . . . . . . . . . . . . 7-3
Programmatic Synthesis Automation . . . . . . . . . . . . . . . . . . 7-5
Properties — Alphabetical List
8
Function Reference
9
x Contents