LTC2433-1 - Differential Input 16-Bit No Latency Delta Sigma ADC

28 Pages·2004·0.29 MB·English

by  Linear Technology Corporation

LTC2433-1
Differential Input
DS
16-Bit No Latency ADC
FEATURES DESCRIPTIOU
n 16-Bit Differential ADC in a Tiny MSOP The LTC®2433-1 is a differential input micropower 16-bit
n Low Supply Current: 200m A, 4m A in Autosleep No Latency SD TM analog-to-digital converter with an inte-
n Rail-to-Rail Differential Input/Reference grated oscillator. It provides 0.12LSB INL and 1.45m V
n 0.12LSB INL, No Missing Codes RMS noise independent of V . It uses delta-sigma
REF
m
n V Offset technology and provides single conversion settling of the
m
n 1.45 V RMS Noise, Independent of V digital filter. Through a single pin, the LTC2433-1 can be
REF
n Very Low Transition Noise: <0.02LSB configured for better than 87dB input differential mode
n Operates with a Reference as Low as 100mV with rejection at 50Hz and 60Hz – 2%, or it can be driven by an
16-Bit Resolution external oscillator for a user defined rejection frequency.
n Internal Oscillator—No External Components The internal oscillator requires no external frequency
Required setting components.
n 87dB Min, Simultaneous 50Hz and 60Hz Notch Filter
The converter accepts any external differential reference
n Single Supply 2.7V to 5.5V Operation
voltage from 0.1V to V for flexible ratiometric and
CC
n Pin Compatible with the 20/24-Bit LTC2431/LTC2411
remote sensing measurement configurations. The full-
n Available in 10-Lead MSOP Package
scale differential input range is from –0.5 •␣V to 0.5 •
REF
APPLICATIOU S VREF. The reference common mode voltage, VREFCM, and
the input common mode voltage, V , may be indepen-
INCM
n Direct Sensor Digitizer CC. The DC
n Weight Scales common mode input rejection is better than 140dB.
n Direct Temperature Measurement
The LTC2433-1 communicates through a flexible 3-wire
n Gas Analyzers
digital interface which is compatible with SPI and
n Strain-Gage Transducers MICROWIRETM protocols.
n Instrumentation
, LTC and LT are registered trademarks of Linear Technology Corporation.
n Data Acquisition No Latency DS is a trademark of Linear Technology Corporation.
n Industrial Process Control MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIOU
Minimum Resolvable Signal vs V
REF
90
5V REF V)* 80
4.9k 1µF 1 VCC FO 10 == EINXTTEERRNNAALL OCSLCO/CSKIM SUOLUTRACNEEOUS µGNAL ( 6700
100Ω (100mV) 42 RINE+F+ 50Hz/60Hz REJECTION ABLE SI 50
LTC2433-1 OLV 40
5 IN– SCK 9 RES 30
M
36 RGENFD– SDCOS 8 3S-PWI IINRTEERFACE MINIMU 2100
24331 TA01 0
0 1 2 3 4 5
REF (V) 24331 TA02
*FOR VREF ‡ 0.5V THE RESOLUTION
IS LIMITED BY STEP SIZE
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V
LTC2433-1
ABSOLUTE W AXIW UW RATIU GS PACKAGE/ORDER IU FORW ATIOU
(Notes 1, 2)
ORDER PART NUMBER
Supply Voltage (V ) to GND.......................–0.3V to 7V
CC
Analog Input Voltage
LTC2433-1CMS
to GND....................................–0.3V to (V + 0.3V) TOP VIEW
CC
LTC2433-1IMS
Reference Input Voltage VCC 1 10 FO
REF+ 2 9 SCK
to GND....................................–0.3V to (V + 0.3V) REF– 3 8 SDO
CC IN+ 4 7 CS
Digital Input Voltage to GND........–0.3V to (VCC + 0.3V) IN– 5 6 GND
MS PART MARKING
Digital Output Voltage to GND .....–0.3V to (V + 0.3V) MS10 PACKAGE
CC
10-LEAD PLASTIC MSOP
Operating Temperature Range
LTC2433-1C............................................0(cid:176) C to 70(cid:176) C TJMAX = 125(cid:176)C, q JA = 110(cid:176)C/W LTAEY
LTAEZ
LTC2433-1I ........................................ –40(cid:176) C to 85(cid:176) C
Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C
Lead Temperature (Soldering, 10 sec)..................300(cid:176) C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25(cid:176) C. (Notes 3, 4, 6)
A
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V £ V £ V , –0.5 • V £ V £ 0.5 • V , (Note 5) l 16 Bits
REF CC REF IN REF
Integral Nonlinearity (Note 15) 5V £ V £ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 0.06 LSB
CC INCM
5V £ V £ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V, (Note 6) l 0.12 1.25 LSB
CC INCM
REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 0.30 LSB
INCM
Offset Error (Note 15) 2.5V £ REF+ £ V , REF– = GND, l 5 20 m V
CC
GND £ IN+ = IN– £ V , (Note 13)
CC
Offset Error Drift 2.5V £ REF+ £ V , REF– = GND, 20 nV/(cid:176) C
CC
GND £ IN+ = IN– £ V
CC
Positive Full-Scale Error (Note 15) 2.5V £ REF+ £ V , REF– = GND, l 0.16 1.25 LSB
CC
IN+ = 0.75REF+, IN– = 0.25 • REF+
Positive Full-Scale Error Drift 2.5V £ REF+ £ V , REF– = GND, 0.04 ppm of V /(cid:176) C
CC REF
IN+ = 0.75REF+, IN– = 0.25 • REF+
Negative Full-Scale Error (Note 15) 2.5V £ REF+ £ V , REF– = GND, l 0.16 1.25 LSB
CC
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Negative Full-Scale Error Drift 2.5V £ REF+ £ V , REF– = GND, 0.04 ppm of V /(cid:176) C
CC REF
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Total Unadjusted Error 5V £ V £ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V 0.20 LSB
CC INCM
5V £ V £ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V 0.20 LSB
CC INCM
REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 0.25 LSB
INCM
Output Noise 5V £ V £ 5.5V, REF+ = 5V, REF– = GND, 1.45 m V
CC RMS
GND £ IN– = IN+ £ V , (Note 12)
CC
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LTC2433-1
COU VERTER CHARACTERISTICS
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25(cid:176) C. (Notes 3, 4)
A
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V £ REF+ £ V , REF– = GND, l 130 140 dB
CC
GND £ IN– = IN+ £ V (Note 5)
CC
Input Common Mode Rejection 2.5V £ REF+ £ V , REF– = GND, l 140 dB
CC
49Hz to 61.2Hz GND £ IN– = IN+ £ V , (Notes 5, 7)
CC
Input Normal Mode Rejection (Note 5, 7) l 87 dB
49Hz to 61.2Hz
Reference Common Mode 2.5V £ REF+ £ V , GND £ REF– £ 2.5V, l 130 140 dB
CC
Rejection DC V = 2.5V, IN– = IN+ = GND (Note 5)
REF
Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB
Power Supply Rejection, REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB
Simultaneous 50Hz/60Hz – 2%
AU ALOG IU PUT AU D REFERE U CE
The l denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3 V + 0.3 V
CC
IN– Absolute/Common Mode IN– Voltage l GND – 0.3 V + 0.3 V
CC
V Input Differential Voltage Range l –V /2 V /2 V
IN REF REF
(IN+ – IN–)
REF+ Absolute/Common Mode REF+ Voltage l 0.1 V V
CC
REF– Absolute/Common Mode REF– Voltage l GND V – 0.1 V
CC
V Reference Differential Voltage Range l 0.1 V V
REF CC
(REF+ – REF–)
C (IN+) IN+ Sampling Capacitance 6 pF
S
C (IN–) IN– Sampling Capacitance 6 pF
S
C (REF+) REF+ Sampling Capacitance 6 pF
S
C (REF–) REF– Sampling Capacitance 6 pF
S
I (IN+) IN+ DC Leakage Current CS = V = 5V, IN+ = GND l –100 1 100 nA
DC_LEAK CC
I (IN–) IN– DC Leakage Current CS = V = 5V, IN– = 5.5V l –100 1 100 nA
DC_LEAK CC
I (REF+) REF+ DC Leakage Current CS = V = 5V, REF+ = 5.5V l –100 1 100 nA
DC_LEAK CC
I (REF–) REF– DC Leakage Current CS = V = 5V, REF– = GND l –100 1 100 nA
DC_LEAK CC
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LTC2433-1
DIGITAL I U PUTS AU D DIGITAL OUTPUTS
The l denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V High Level Input Voltage 2.7V £ V £ 5.5V l 2.5 V
IH CC
CS, F 2.7V £ V £ 3.3V 2.0 V
O CC
V Low Level Input Voltage 4.5V £ V £ 5.5V l 0.8 V
IL CC
CS, F 2.7V £ V £ 5.5V 0.6 V
O CC
V High Level Input Voltage 2.7V £ V £ 5.5V (Note 8) l 2.5 V
IH CC
SCK 2.7V £ V £ 3.3V (Note 8) 2.0 V
CC
V Low Level Input Voltage 4.5V £ V £ 5.5V (Note 8) l 0.8 V
IL CC
SCK 2.7V £ V £ 5.5V (Note 8) 0.6 V
CC
I Digital Input Current 0V £ V £ V l –10 10 m A
IN IN CC
CS, F
O
I Digital Input Current 0V £ V £ V (Note 8) l –10 10 m A
IN IN CC
SCK
C Digital Input Capacitance 10 pF
IN
CS, F
O
C Digital Input Capacitance (Note 8) 10 pF
IN
SCK
V High Level Output Voltage I = –800m A l V – 0.5 V
OH O CC
SDO
V Low Level Output Voltage I = 1.6mA l 0.4 V
OL O
SDO
V High Level Output Voltage I = –800m A (Note 9) l V – 0.5 V
OH O CC
SCK
V Low Level Output Voltage I = 1.6mA (Note 9) l 0.4 V
OL O
SCK
I Hi-Z Output Leakage l –10 10 m A
OZ
SDO
POWER REQUIREW E U TS
The l denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25(cid:176) C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V Supply Voltage l 2.7 5.5 V
CC
I Supply Current
CC
Conversion Mode CS = 0V (Note 14) l 200 300 m A
Sleep Mode CS = V (Notes 11, 14) l 4 13 m A
CC
Sleep Mode CS = V , 2.7V £ V £ 3.3V 2 m A
CC CC
(Notes 11, 14)
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LTC2433-1
TI W I U G CHARACTERISTICS
The l denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25(cid:176) C. (Note 3)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f External Oscillator Frequency Range l 2.56 2000 kHz
EOSC
t External Oscillator High Period l 0.25 390 m s
HEO
t External Oscillator Low Period l 0.25 390 m s
LEO
t Conversion Time F = 0V l 143.8 146.7 149.6 ms
CONV O
External Oscillator (Note 10) l 20510/f (in kHz) ms
EOSC
f Internal SCK Frequency Internal Oscillator (Note 9) 17.5 kHz
ISCK
External Oscillator (Notes 9, 10) f /8 kHz
EOSC
D Internal SCK Duty Cycle (Note 9) l 45 55 %
ISCK
f External SCK Frequency Range (Note 8) l 2000 kHz
ESCK
t External SCK Low Period (Note 8) l 250 ns
LESCK
t External SCK High Period (Note 8) l 250 ns
HESCK
t Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 1.06 1.09 1.11 ms
DOUT_ISCK
External Oscillator (Notes 9, 10) l 152/f (in kHz) ms
EOSC
t External SCK 19-Bit Data Output Time (Note 8) l 19/f (in kHz) ms
DOUT_ESCK ESCK
t CS fl to SDO Low Z l 0 200 ns
1
t2 CS › to SDO High Z l 0 200 ns
t3 CS fl to SCK fl (Note 9) l 0 200 ns
t4 CS fl to SCK › (Note 8) l 50 ns
t SCK fl to SDO Valid l 220 ns
KQMAX
t SDO Hold After SCK fl (Note 5) l 15 ns
KQMIN
t SCK Set-Up Before CS fl l 50 ns
5
t SCK Hold After CS fl l 50 ns
6
Note 1: Absolute Maximum Ratings are those values beyond which the Note 9: The converter is in internal SCK mode of operation such that
life of the device may be impaired. the SCK pin is used as digital output. In this mode of operation the
Note 2: All voltage values are with respect to GND. SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified. Note 10: The external oscillator is connected to the FO pin. The external
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–, oscillator frequency, fEOSC, is expressed in kHz.
V = (IN+ + IN–)/2. Note 11: The converter uses the internal oscillator.
INCM
Note 4: FO pin tied to GND or to an external conversion clock source FO = 0V.
with f = 139,800Hz unless otherwise specified. Note 12: 1.45m V RMS noise is independent of V . Since the noise
EOSC REF
Note 5: Guaranteed by design, not subject to test. performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by Note 13: Guaranteed by design and test correlation.
the LSB step size (V /216) and the single shot measurement. Typical Note 14: The low sleep mode current is valid only when CS is high.
REF
specifications are measured from the center of the quantization band. Note 15: These parameters are guaranteed by design over the full
Note 7: F = GND (internal oscillator) or f = 139,800Hz – 2% supply and temperature range. Automated testing procedures are
O EOSC
(external oscillator). limited by the LSB step size (V /65,536).
REF
Note 8: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f and is expressed in kHz.
ESCK
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LTC2433-1
PIU FUU CTIOU S
V (Pin 1): Positive Supply Voltage. Bypass to GND with SDO (Pin 8): Three-State Digital Output. During the Data
CC
a 10m F tantalum capacitor in parallel with 0.1m F ceramic Output period, this pin is used as serial data output. When
capacitor as close to the part as possible. the chip select CS is HIGH (CS = V ) the SDO pin is in a
CC
high impedance state. During the Conversion and Sleep
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
periods, this pin is used as the conversion status output.
The voltage on these pins can have any value between GND
The conversion status can be observed by pulling CS LOW.
and V as long as the reference positive input, REF+, is
CC
maintained more positive than the reference negative SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
input, REF–, by at least 0.1V. Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
Output period. In External Serial Clock Operation mode,
voltage on these analog inputs can have any value between
SCK is used as digital input for the external serial interface
GND and V . Within these limits the converter bipolar
CC
clock during the Data Output period. A weak internal pull-
input range (V = IN+ – IN–) extends from –0.5 • (V )
IN REF
up is automatically activated in Internal Serial Clock Op-
to 0.5 • (V ). Outside this input range the converter
REF
eration mode. The Serial Clock Operation mode is deter-
produces unique overrange and underrange output codes.
mined by the logic level applied to the SCK pin at power up
GND (Pin 6): Ground. Connect this pin to a ground plane or during the most recent falling edge of CS.
through a low impedance connection.
F (Pin 10): Frequency Control Pin. Digital input that
O
CS (Pin 7): Active LOW Digital Input. A LOW on this pin controls the ADC’s notch frequencies and conversion
enables the SDO digital output and wakes up the ADC. time. When the F pin is connected to GND (F = 0V), the
O O
Following each conversion the ADC automatically enters converter uses its internal oscillator and rejects 50Hz and
the Sleep mode and remains in this low power state as 60Hz simultaneously. When F is driven by an external
O
long as CS is HIGH. A LOW-to-HIGH transition on CS clock signal with a frequency f , the converter uses this
EOSC
during the Data Output transfer aborts the data transfer signal as its system clock and the digital filter has 87dB
and starts a new conversion. minimum rejection in the range f /2560 – 14% and
EOSC
110dB minimum rejection at f /2560 – 4%.
EOSC
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LTC2433-1
FUU CTIOU AL DIAGRAW
INTERNAL
VCC OSCILLATOR
GND AUTOCALIBRATION
AND CONTROL FO
(INT/EXT)
IN+ +∫ ∫ ∫
IN– –
SDO
∑
SERIAL
ADC SCK
INTERFACE
CS
DECIMATING FIR
DAC
24331 FD
REF+
REF–
Figure 1. Functional Block Diagram
TEST CIRCUITS
VCC
1.69k
SDO SDO
1.69k CLOAD = 20pF CLOAD = 20pF
Hi-Z TO VOH Hi-Z TO VOL
VOL TO VOH VOH TO VOL
VOH TO Hi-Z 24361 TA03 VOL TO Hi-Z 24361 TA04
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LTC2433-1
APPLICATIOU S IU FORW ATIOU
CONVERTER OPERATION conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
Converter Operation Cycle formed. This result is shifted out on the serial data out pin
The LTC2433-1 is a low power, SD ADC with differential (SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
input/reference and an easy-to-use 3-wire serial interface
reliably latch data on the rising edge of SCK (see Figure 3).
(see Figure 1). Its operation is made up of three states.
The data output state is concluded once 19 bits are read
The converter operating cycle begins with the conversion,
out of the ADC or when CS is brought HIGH. The device
followed by the low power sleep state and ends with the
automatically initiates a new conversion and the cycle
data output (see Figure 2). The 3-wire interface consists
repeats. In order to maintain compatibility with 24-/32-bit
of serial data output (SDO), serial clock (SCK) and chip
data transfers, it is possible to clock the LTC2433-1 with
select (CS).
additional serial clock pulses. This results in additional
Initially, the LTC2433-1 performs a conversion. Once the
data bits which are logic HIGH.
conversion is complete, the device enters the sleep state.
Through timing control of the CS and SCK pins, the
The part remains in the sleep state as long as CS is HIGH.
LTC2433-1 offers several flexible modes of operation
While in this sleep state, power consumption is reduced by
(internal or external SCK and free-running conversion
nearly two orders of magnitude. The conversion result is
modes). These various modes do not require program-
held indefinitely in a static shift register while the converter
ming configuration registers; moreover, they do not dis-
is in the sleep state.
turb the cyclic operation described above. These modes of
Once CS is pulled LOW, the device exits the low power
operation are described in detail in the Serial Interface
mode and enters the data output state. If CS is pulled HIGH
Timing Modes section.
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still Conversion Clock
held in the internal static shift register. If CS remains LOW
A major advantage the delta-sigma converter offers over
after the first rising edge of SCK, the device begins
conventional type converters is an on-chip digital filter
outputting the conversion result. Taking CS high at this
(commonly implemented as a Sinc or Comb filter). For
point will terminate the data output state and start a new
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor-
CONVERT
mance is directly related to the accuracy of the converter
system clock. The LTC2433-1 incorporates a highly accu-
SLEEP rate on-chip oscillator. This eliminates the need for exter-
nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
FALSE CS = LOW LTC2433-1 achieves a minimum of 87dB rejection over
AND
SCK the range 49Hz to 61.2Hz.
TRUE
Ease of Use
DATA OUTPUT
24331 F02 The LTC2433-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
Figure 2. LTC2433-1 State Transition Diagram multiple analog voltages is easy.
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LTC2433-1
APPLICATIOU S IU FORW ATIOU
The LTC2433-1 performs offset and full-scale calibrations remains constant at 1.45m V RMS (or 8.7m V ), while the
P-P
every conversion cycle. This calibration is transparent to quantization is reduced to 1.5m V per LSB. As a result,
the user and has no effect on the cyclic operation de- lowering the reference improves the effective resolution
scribed above. The advantage of continuous calibration is for low level input voltages.
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift. Input Voltage Range
The analog input is truly differential with an absolute/
Power-Up Sequence
common mode range for the IN+ and IN– input pins
The LTC2433-1 automatically enters an internal reset state extending from GND – 0.3V to V + 0.3V. Outside these
CC
when the power supply voltage V drops below approxi- limits, the ESD protection devices begin to turn on and the
CC
mately 2V. This feature guarantees the integrity of the errors due to input leakage current increase rapidly. Within
conversion result and of the serial interface mode selec- these limits, the LTC2433-1 converts the bipolar differen-
tion. (See the 2-wire I/O sections in the Serial Interface tial input signal, V = IN+ – IN–, from –FS = –0.5 • V to
IN REF
Timing Modes section.) +FS = 0.5 • V where V = REF+ – REF–. Outside this
REF REF
range, the converter indicates the overrange or the
When the V voltage rises above this critical threshold,
CC
underrange condition using distinct output codes.
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears Input signals applied to the analog input pins may extend
all internal registers. Following the POR signal, the by 300mV below ground and above V . In order to limit
CC
LTC2433-1 starts a normal conversion cycle and follows any fault current, resistors of up to 5k may be added in
the succession of states described above. The first con- series with the pins without affecting the performance of
version result following POR is accurate within the speci- the device. In the physical layout, it is important to main-
fications of the device if the power supply voltage is restored tain the parasitic capacitance of the connection between
within the operating range (2.7V to 5.5V) before the end of these series resistors and the corresponding pins as low
the POR time interval. as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
Reference Voltage Range resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
This converter accepts a truly differential external refer-
Current sections. In addition, series resistors will intro-
ence voltage. The absolute/common mode voltage speci-
fication for the REF+ and REF– pins covers the entire range duce a temperature dependent offset error due to the input
leakage current. A 10nA input leakage current will develop
from GND to V . For correct converter operation, the
CC
REF+ pin must always be more positive than the REF– pin. a 1LSB offset error on an 8k resistor if VREF = 5V. This error
has a very strong temperature dependency.
The LTC2433-1 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is deter- Output Data Format
mined by the thermal noise of the front-end circuits, and
The LTC2433-1 serial output data stream is 19 bits long.
as such, its value in microvolts is nearly constant with
The first 3 bits represent status information indicating the
reference voltage. A decrease in reference voltage will
conversion state and sign. The next 16 bits are the conver-
significantly improve the converter’s effective resolution,
sion result, MSB first. The third and fourth bit together are
since the thermal noise (1.45m V) is well below the quan-
also used to indicate an underrange condition (the differ-
tization level of the device (75.6m V for a 5V reference). At
ential input voltage is below –FS) or an overrange condi-
the minimum reference (100mV) the thermal noise
tion (the differential input voltage is above +FS).
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LTC2433-1
APPLICATIOU S IU FORW ATIOU
Bit 18 (first output bit) is the end of conversion (EOC) SCK clock pulses are ignored by the internal data out shift
indicator. This bit is available at the SDO pin during the register.
conversion and sleep states whenever the CS pin is LOW.
In order to shift the conversion result out of the device, CS
This bit is HIGH during the conversion and goes LOW
must first be driven LOW. EOC is seen at the SDO pin of the
when the conversion is complete.
device once CS is pulled LOW. EOC changes real time from
Bit 17 (second output bit) is a dummy bit (DMY) and is HIGH to LOW at the completion of a conversion. This
always LOW. signal may be used as an interrupt for an external micro-
controller. Bit 18 (EOC) can be captured on the first rising
Bit 16 (third output bit) is the conversion result sign indi-
edge of SCK. Bit 17 is shifted out of the device on the first
cator (SIG). If V is >0, this bit is HIGH. If V is <0, this
IN IN
falling edge of SCK. The final data bit (Bit 0) is shifted out
bit is LOW.
on the falling edge of the 18th SCK and may be latched on
Bit 15 (fourth output bit) is the most significant bit (MSB) the rising edge of the 19th SCK pulse. On the falling edge
of the result. This bit in conjunction with Bit 16 also of the 19th SCK pulse, SDO goes HIGH indicating the
provides the underrange or overrange indication. If both initiation of a new conversion cycle. This bit serves as EOC
Bit 16 and Bit 15 are HIGH, the differential input voltage is (Bit 18) for the next conversion cycle. Table 2 summarizes
above +FS. If both Bit 16 and Bit 15 are LOW, the the output data format.
differential input voltage is below –FS.
In order to remain compatible with some SPI
The function of these bits is summarized in Table 1. microcontrollers, more than 19 SCK clock pulses may be
applied. As long as these clock edges are complete before
Table 1. LTC2433-1 Status Bits
the conversion ends, they will not effect the serial data.
Bit 18 Bit 17 Bit 16 Bit 15
Input Range EOC DMY SIG MSB However, switching SCK during a conversion may gener-
V ‡ 0.5 • V 0 0 1 1 ate ground currents in the device leading to extra offset
IN REF
0V £ V < 0.5 • V 0 0 1 0 and noise error sources.
IN REF
–0.5 • VREF £ VIN < 0V 0 0 0 1 As long as the voltage on the analog input pins is main-
VIN < –0.5 • VREF 0 0 0 0 tained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
Bits 15-0 are the 16-Bit conversion result MSB first.
differential input voltage V from –FS = –0.5 • V to
IN REF
Bit 0 is the least significant bit (LSB). +FS = 0.5 • V . For differential input voltages greater than
REF
+FS, the conversion result is clamped to the value corre-
Data is shifted out of the SDO pin under control of the serial
sponding to the +FS + 1LSB. For differential input voltages
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
below –FS, the conversion result is clamped to the value
remains high impedance and any externally generated
corresponding to –FS – 1LSB.
CS
BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 1 BIT 0
SDO EOC “O” SIG MSB LSB16
Hi-Z
SCK
1 2 3 4 5 17 18 19
SLEEP DATA OUTPUT CONVERSION
24331 F03
Figure 3. Output Data Timing
24331fa
10