LTC2325-12 - Quad, 12-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC PDF
Preview LTC2325-12 - Quad, 12-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC
LTC2325-12 Quad, 12-Bit + Sign, 5Msps/Ch Simultaneous Sampling ADC FeaTures DescripTion n 5Msps/Ch Throughput Rate The LTC®2325-12 is a low noise, high speed quad 12-bit n Four Simultaneously Sampling Channels + sign successive approximation register (SAR) ADC with n Guaranteed 12-Bit, No Missing Codes differential inputs and wide input common mode range. n 8V Differential Inputs with Wide Input Operating from a single 3.3V or 5V supply, the LTC2325-12 P-P Common Mode Range has an 8V differential input range, making it ideal for P-P n 77dB SNR (Typ) at f = 2.2MHz applications which require a wide dynamic range with IN n –86dB THD (Typ) at f = 2.2MHz high common mode rejection. The LTC2325-12 achieves IN n Guaranteed Operation to 125°C ±0.5LSB INL typical, no missing codes at 12 bits and n Single 3.3V or 5V Supply 77dB SNR. n Low Drift (20ppm/°C Max) 2.048V or 4.096V The LTC2325-12 has an onboard low drift (20ppm/°C max) Internal Reference 2.048V or 4.096V temperature-compensated reference. n 1.8V to 2.5V I/O Voltages The LTC2325-12 also has a high speed SPI-compatible n CMOS or LVDS SPI-Compatible Serial I/O serial interface that supports CMOS or LVDS. The fast n Power Dissipation 45mW/Ch (Typ) 5Msps per channel throughput with one cycle latency n Small 52-Lead (7mm × 8mm) QFN Package makes the LTC2325-12 ideally suited for a wide variety of high speed applications. The LTC2325-12 dissipates applicaTions only 45mW per channel and offers nap and sleep modes to reduce the power consumption to 26μW for further n High Speed Data Acquisition Systems power savings during inactive periods. n Communications n Optical Networking L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Analog Devices, Inc. All other trademarks are the property of their n Multiphase Motor Control respective owners. Typical applicaTion 32k Point FFT f = 5Msps, TRUE DIFFERENTIAL INPUTS 10µF 1µF SMPL f = 2.2MHz NO CONFIGURATION REQUIRED 3.3V OR 5V 1.8V TO 2.5V IN IN+, IN– 0 SNR = 77.1dB ARBITRARY DIFFERENTIAL VDD GND GND OVDD THD = –85.7dB VDD VDD AAIINN11+– S/H S1A+2SR-I BGAINDTC CMSODSR/L/DVDDRS –20 SSIFNDARD = = 9 706.3.2ddBB –40 REFBUFEN S) 0V 0V AAIINN22+– S/H S1A+2SR-I BGAINDTC SSDDOO12 E (dBF –60 D SDO3 U VDD BIPOLAR VDD UNIPOLAR AAIINN33+– SL/THC2325-1S21A+2SR-I BGAINDTC CLKSODSCUOKT4 AMPLIT–1–0800 CNV SAMPLE 0V 0V AAIINN44+– S/H S1A+2SR-I BGAINDTC CLOCK –120 –140 REF REFOUT1 REFOUT2 REFOUT3 REFOUT4 0 0.5 1 1.5 2 2.5 FOUR SIMULTANEOUS 1µF 10µF 10µF 10µF 10µF FREQUENCY (MHz) SAMPLING CHANNELS 232512 TA01a 232512 TA01b 232512f 1 For more information www.linear.com/LTC2325-12 LTC2325-12 absoluTe MaxiMuM raTings pin conFiguraTion (Notes 1, 2) Supply Voltage (V ) ..................................................6V TOP VIEW DD ASunpalpolgy VInopltuatg Veo (lOtaVgDeD ) ................................................3V VDD NC NC GND NC NC GND REFOUT4 VDD REFBUFEN–DNC/SCK+SCK/SCK AIN+, AIN– (Note 3) ...................–0.3V to (VDD + 0.3V) AIN4– 1 52 51 50 49 48 47 46 45 44 43 42 41 40 DNC/SDOD– REFOUT1,2,3,4.........................–0.3V to (V + 0.3V) DD AIN4+ 2 39 SDO4/SDOD+ CNV........................................–0.3V to (OVDD + 0.3V) GND 3 38 GND Digital Input Voltage AIN3– 4 37 OVDD (Note 3) ..........................(GND – 0.3V) to (OV + 0.3V) AIN3+ 5 36 DNC/SDOC– DD REFOUT3 6 35 SDO3/SDOC+ Digital Output Voltage GND 7 34 CLKOUTEN/CLKOUT– 53 (Note 3) ..........................(GND – 0.3V) to (OVDD + 0.3V) REF 8 GND 33 CLKOUT/CLKOUT+ Operating Temperature Range REFOUT2 9 32 GND LTC2325C ................................................0°C to 70°C AIN2– 10 31 OVDD AIN2+ 11 30 DNC/SDOB– LTC2325I .............................................–40°C to 85°C GND 12 29 SDO2/SDOB+ LTC2325H ..........................................–40°C to 125°C AIN1– 13 28 DNC/SDOA– Storage Temperature Range ..................–65°C to 150°C AIN1+ 14 27 SDO1/SDOA+ 15 16 17 18 19 20 21 22 23 24 25 26 D C C D C C D 1 R V S D VD N N GN N N VD REFOUT SDR/DD CN MOS/LVD GN C UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 31°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion http://www.linear.com/product/LTC2325-12#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2325CUKG-12#PBF LTC2325CUKG-12#TRPBF LTC2325UKG-12 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C LTC2325IUKG-12#PBF LTC2325IUKG-12#TRPBF LTC2325UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C LTC2325HUKG-12#PBF LTC2325HUKG-12#TRPBF LTC2325UKG-12 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 232512f 2 For more information www.linear.com/LTC2325-12 LTC2325-12 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN+ Absolute Input Range (AIN+ to AIN–) (Note 5) l 0 VDD V VIN– Absolute Input Range (AIN+ to AIN–) (Note 5) l 0 VDD V VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– l –REFOUT1,2,3,4 REFOUT1,2,3,4 V VCM Common Mode Input Range VCM = (VIN+ – VIN–)/2 l 0 VDD V I Analog Input DC Leakage Current l –1 1 μA IN C Analog Input Capacitance 10 pF IN CMRR Input Common Mode Rejection Ratio f = 2.2MHz 102 dB IN V CNV High Level Input Voltage l 1.5 V IHCNV V CNV Low Level Input Voltage l 0.5 V ILCNV I CNV Input Current l –10 10 μA INCNV converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution l 12 Bits No Missing Codes l 12 Bits Transition Noise 0.3 LSB RMS INL Integral Linearity Error (Note 6) l –1 ±0.5 1 LSB DNL Differential Linearity Error l –0.99 ±0.4 0.99 LSB BZE Bipolar Zero-Scale Error (Note 7) l –1 0 1 LSB Bipolar Zero-Scale Error Drift 0.01 LSB/°C FSE Bipolar Full-Scale Error V = 4.096V (REFBUFEN Grounded) (Note 7) l –2 2 LSB REFOUT1,2,3,4 Bipolar Full-Scale Error Drift V = 4.096V (REFBUFEN Grounded) 15 ppm/°C REFOUT1,2,3,4 232512f 3 For more information www.linear.com/LTC2325-12 LTC2325-12 DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C and A = –1dBFS (Notes 4, 8). A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio f = 2.2MHz, V = 4.096V, Internal Reference l 74 76 dB IN REFOUT1,2,3,4 f = 2.2MHz, V = 5V, External Reference 76.5 dB IN REFOUT1,2,3,4 SNR Signal-to-Noise Ratio f = 2.2MHz, V = 4.096V, Internal Reference l 75 77 dB IN REFOUT1,2,3,4 f = 2.2MHz, V = 5V, External Reference 77.6 dB IN REFOUT1,2,3,4 THD Total Harmonic Distortion f = 2.2MHz, V = 4.096V, Internal Reference l –86 –76 dB IN REFOUT1,2,3,4 f = 2.2MHz, V = 5V, External Reference –85 dB IN REFOUT1,2,3,4 SFDR Spurious Free Dynamic Range f = 2.2MHz, V = 4.096V, Internal Reference l 76 93 dB IN REFOUT1,2,3,4 f = 2.2MHz, V = 5V, External Reference 93 dB IN REFOUT1,2,3,4 –3dB Input Bandwidth 95 MHz Aperture Delay 500 ps Aperture Delay Matching 500 ps Aperture Jitter 1 ps RMS Transient Response Full-Scale Step 30 ns inTernal reFerence characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Internal Reference Output Voltage 4.75V < V < 5.25V l 4.078 4.096 4.115 V REFOUT1,2,3,4 DD 3.13V < V < 3.47V l 2.034 2.048 2.064 V DD V Temperature Coefficient (Note 14) l 3 20 ppm/°C REF REFOUT1,2,3,4 Output Impedance 0.25 Ω V Line Regulation 4.75V < V < 5.25V 0.3 mV/V REFOUT1,2,3,4 DD I External Reference Current REFBUFEN = 0V REFOUT1,2,3,4 REFOUT1,2,3,4 = 4.096V 500 μA REFOUT1,2,3,4 = 2.048V 300 μA (Notes 9, 10) 232512f 4 For more information www.linear.com/LTC2325-12 LTC2325-12 DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Digital Inputs and Outputs CMOS/LVDS = GND V High Level Input Voltage l 0.8 • OV V IH DD V Low Level Input Voltage l 0.2 • OV V IL DD I Digital Input Current V = 0V to OV l –10 10 μA IN IN DD C Digital Input Capacitance l 5 pF IN V High Level Output Voltage I = –500μA l OV – 0.2 V OH O DD V Low Level Output Voltage I = 500μA l 0.2 V OL O I Hi-Z Output Leakage Current V = 0V to OV l –10 10 μA OZ OUT DD I Output Source Current V = 0V l –10 mA SOURCE OUT I Output Sink Current V = OV l 10 mA SINK OUT DD LVDS Digital Inputs and Outputs CMOS/LVDS = OV DD V LVDS Differential Input Voltage 100Ω Differential Termination l 240 600 mV ID OV = 2.5V DD V LVDS Common Mode Input Voltage 100Ω Differential Termination l 1 1.45 V IS OV = 2.5V DD V LVDS Differential Output Voltage 100Ω Differential Termination l 220 350 600 mV OD OV = 2.5V DD V LVDS Common Mode Output Voltage 100Ω Differential Termination l 0.85 1.2 1.4 V OS OV = 2.5V DD V Low Power LVDS Differential Output 100Ω Differential Termination l 100 200 350 mV OD_LP Voltage OV = 2.5V DD V Low Power LVDS Common Mode Output 100Ω Differential Termination l 0.85 1.2 1.4 V OS_LP Voltage OV = 2.5V DD 232512f 5 For more information www.linear.com/LTC2325-12 LTC2325-12 power requireMenTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage 5V Operation l 4.75 5.25 V DD 3.3V Operation l 3.13 3.47 V IV Supply Current 5Msps Sample Rate (IN+ = IN– = 0V) l 31 44.5 mA DD CMOS I/O Mode: CMOS/LVDS = GND OV Supply Voltage l 1.71 2.63 V DD I Supply Current 5Msps Sample Rate (C = 5pF) l 4.4 15.5 mA OVDD L I Nap Mode Current Conversion Done (I ) l 5.3 6.4 mA NAP VDD I Sleep Mode Current Sleep Mode (I + I ) l 20 90 µA SLEEP VDD OVDD P Power Dissipation V = 3.3V, 5Msps Sample Rate l 102 181 mW D_3.3V DD Nap Mode l 18 21.1 mW Sleep Mode l 20 288 µW P Power Dissipation V = 5V, 5Msps Sample Rate l 162 261 mW D_5V DD Nap Mode l 27 32 mW Sleep Mode l 30 424 µW LVDS I/O Mode: CMOS/LVDS = OV , OV = 2.5V DD DD OV Supply Voltage l 2.37 2.63 V DD I Supply Current 5Msps Sample Rate (C = 5pF, R = 100Ω) l 26 32 mA OVDD L L I Nap Mode Current Conversion Done (I ) l 5.3 6.4 mA NAP VDD I Sleep Mode Current Sleep Mode (I + I ) l 20 90 µA SLEEP VDD OVDD P Power Dissipation V = 3.3V, 5Msps Sample Rate l 151 218 mW D_3.3V DD Nap Mode l 52 58.6 mW Sleep Mode l 80 288 µW P Power Dissipation V = 5V, 5Msps Sample Rate l 214 303 mW D_5V DD Nap Mode l 50 69.2 mW Sleep Mode l 40 424 µW aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f Maximum Sampling Frequency l 5 Msps SMPL t Time Between Conversions (Note 11) t = t + t l 0.2 1000 µs CYC CYC CNVH CONV t Conversion Time l 170 ns CONV t CNV High Time l 30 ns CNVH t Sampling Aperture (Note 11) t = t – t 28 ns ACQUISITION ACQUISITION CYC CONV t REFOUT1,2,3,4 Wake-Up Time C = 10µF 50 ms WAKE REFOUT1,2,3,4 CMOS I/O Mode: SDR, CMOS/LVDS = GND, SDR/ DDR = GND t SCK Period (Note 13) l 9.1 ns SCK t SCK High Time l 4.1 ns SCKH t SCK Low Time l 4.1 ns SCKL tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns t SCK to CLKOUT Delay (Note 12) l 2.5 4.5 ns DSCKCLKOUT 232512f 6 For more information www.linear.com/LTC2325-12 LTC2325-12 aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 4). A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns CMOS I/O Mode: DDR, CMOS/LVDS = GND, SDR/ DDR = OV DD t SCK Period l 18.2 ns SCK t SCK High Time l 8.2 ns SCKH t SCK Low Time l 8.2 ns SCKL tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns t SCK to CLKOUT Delay (Note 12) l 2 4.5 ns DSCKCLKOUT tDCNVSDOZ Bus Relinquish Time After CNV↑ (Note 11) l 3 ns tDCNVSDOV SDO Valid Delay from CNV↓ (Note 11) l 3 ns tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns LVDS I/O Mode: SDR, CMOS/LVDS = OV , SDR/DDR = GND DD t SCK Period l 9.1 ns SCK t SCK High Time l 4.1 ns SCKH t SCK Low Time l 4.1 ns SCKL tHSDO_SDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns t SCK to CLKOUT Delay (Note 12) l 2 4 ns DSCKCLKOUT tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns LVDS I/O Mode: DDR, CMOS/LVDS = OV , SDR/DDR = OV = 2.5V DD DD t SCK Period l 18.2 ns SCK t SCK High Time l 8.2 ns SCKH t SCK Low Time l 8.2 ns SCKL tHSDO_DDR SDO Data Remains Valid Delay from CLKOUT↓ CL = 5pF (Note 12) l 0 1.5 ns t SCK to CLKOUT Delay (Note 12) l 2 4 ns DSCKCLKOUT tDSCKHCNVH SCK Delay Time to CNV↑ (Note 11) l 0 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings untrimmed deviation from ideal first and last code transitions and includes may cause permanent damage to the device. Exposure to any Absolute the effect of offset error. Maximum Rating condition for extended periods may affect device Note 8: All specifications in dB are referred to a full-scale ±4.096V input reliability and lifetime. with REF = 4.096V. Note 2: All voltage values are with respect to ground. Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer Note 3: When these pin voltages are taken below ground, or above V or must be turned off by setting REFBUFEN = 0V. DD OVDD, they will be clamped by internal diodes. This product can handle input Note 10: fSMPL = 5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate. currents up to 100mA below ground, or above V or OV , without latch-up. DD DD Note 11: Guaranteed by design, not subject to test. Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.096V, f = 5MHz. DD DD SMPL Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V. DD DD Note 5: Recommended operating conditions. Note 13: t of 9.1ns allows a shift clock frequency up to 105MHz for SCK Note 6: Integral nonlinearity is defined as the deviation of a code from a rising edge capture. straight line passing through the actual endpoints of the transfer curve. Note 14: Temperature coefficient is calculated by dividing the maximum The deviation is measured from the center of the quantization band. change in output voltage by the specified temperature range. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB Note 15: CNV is driven from a low jitter digital source, typically at OV DD when the output code flickers between 0 0000 0000 0000 and 1 1111 logic levels. 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS 232512f 7 For more information www.linear.com/LTC2325-12 LTC2325-12 aDc TiMing characTerisTics 0.8 • OVDD tWIDTH 0.2 • OVDD tDELAY tDELAY 50% 50% 0.8 • OVDD 0.8 • OVDD 232512 F01 0.2 • OVDD 0.2 • OVDD Figure 1. Voltage Levels for Timing Specifications 232512f 8 For more information www.linear.com/LTC2325-12 LTC2325-12 Typical perForMance characTerisTics T = 25°C, V = 5V, OV = 2.5V, REFOUT1,2,3,4 A DD DD = 4.096V, f = 5Msps, unless otherwise noted. SMPL Integral Nonlinearity Differential Nonlinearity vs Output Code vs Output Code DC Histogram 1.0 1.0 200000 σ = 0.3 160000 0.5 0.5 INL ERROR (LSB) 0 DNL ERROR (LSB) 0 COUNTS18200000000 –0.5 –0.5 40000 –1.0 –1.0 0 –4096 –2048 0 2048 4096 –4096 –2048 0 2048 4096 –3 –2 –1 0 1 2 3 OUTPUT CODE OUTPUT CODE CODE 232512 G01 232512 G02 232512 G03 32k Point FFT, f = 5Msps, SNR, SINAD vs Input Frequency THD, Harmonics vs Input SMPL f = 2.2MHz (1kHz to 2.2MHz) Frequency (1kHz to 2.2MHz) IN 0 78.0 –80 SNR = 77.1dB THD = –85.7dB 77.7 –84 MPLITUDE (dBFS) ––––86420000 SSIFNDARD = = 9 706.3.2ddBB SINAD LEVEL (dBFS) 7777766677.....25814 SNR SINAD RMONICS LEVEL (dBFS)––11–––0099840628 HD3 THHDD2 A–100 SNR, 7755..69 HD, HA––111028 –120 T 75.3 –116 –140 75.0 –120 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 232512 G04 232512 G05 232512 G06 THD, Harmonics vs Input Common SNR, SINAD vs Reference Voltage, 32k Point FFT, IMD, f = 5Msps, SMPL Mode f = 2.2MHz A + = 1.2MHz, A – = 2.2MHz IN IN IN –80 78 0 f = 2.2MHz f = 2.2MHz SNR THD = 85dB –83 77 –20 VCM = 1MHz, 4VP-P CS LEVEL (dBFS) ––––99885296 HD3THD LEVEL (dBFS) 777456 SINAD DE (dBFS) ––6400 RMONI –98 SINAD 73 MPLITU –80 HA–101 R, A–100 HD, –104 HD2 SN 72 T–107 71 –120 –110 70 –140 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 INPUT COMMON MODE (V) VREFOUT(V) FREQUENCY (MHz) 232512 G07 232512 G08 232512 G09 232512f 9 For more information www.linear.com/LTC2325-12 LTC2325-12 Typical perForMance characTerisTics T = 25°C, V = 5V, OV = 2.5V, REFOUT1,2,3,4 A DD DD = 4.096V, f = 5Msps, unless otherwise noted. SMPL Step Response CMRR vs Input Frequency Crosstalk vs Input Frequency (Large Signal Settling) 120 –105 4096 VCM = 4VP-P –107 112 –109 3072 B)–111 SB) CMRR (dB)19064 CROSSTALK (d––––111111119753 UTPUT CODE (L 12002448 4.096V RANGE O 88 –121 0 –123 IN+ = 5MHz SQUARE WAVE IN– = 0V 80 –125 –1024 0 500 1000 1500 2000 2500 0 0.5 1 1.5 2 2.5 –20–10 0 10 20 30 40 50 60 70 80 90 FREQUENCY (kHz) FREQUENCY (MHz) SETTLING TIME (ns) 232512 G10 232512 G11 232512 G12 Step Response External Reference Supply (Fine Settling) Current vs Sample Frequency REF Output vs Temperature 20 700 1.00 4.096V RANGE REFBUFEN = 0V NAL VALUE (LSB) 10 IINN+– == 05SVMQUHAz RE WAVE RENT (uA)456000000 (OEVXETR RDERFI VBIUNFG REF BUF) RROR (mV)–00..55000 VDD = 3.3V DEVIATION FROM FI–100 SUPPLY CUR123000000 VREFOUT1,2,3,4 = 4.09V6RVEFOUT1,2,3,4 = 2.048V REF OUTPUT E––––2211....50500000 VDD = 5V –20 0 –3.00 –20–10 0 10 20 30 40 50 60 70 80 90 0 1 2 3 4 5 –55 –35 –15 5 25 45 65 85 105 125 SETTLING TIME (ns) SAMPLE FREQUENCY (Msps) TEMPERATURE (°C) 232512 G13 232512 G14 232512 G15 Supply Current OV Current vs SCK Frequency, DD Offset Error vs Temperature vs Sample Frequency C = 10pF LOAD 1.0 40 8 32 FULL SCALE SINUSOIDAL INPUT 30 7 LVDS SB 0.05 RRENT (mA)3305 VDD = 5V NT CMOS (mA) 456 CMOS(2.5V) 22222468DDOV CURREN L LY CU25 VDD = 3.3V URRE 3 CMOS(1.8V) 20 T LVD P C S –0.5 SUP VDD 2 18 (mA 20 O 16 ) 1 LOW POWER LVDS 14 –1.0 15 0 12 –55 –35 –15 5 25 45 65 85 105 125 0 1 2 3 4 5 0 22 44 66 88 110 TEMPERATURE (°C) SAMPLE FREQUENCY (Msps) SCK FREQUENCY (MHz) 232512 G16 232512 G17 232512 G18 232512f 10 For more information www.linear.com/LTC2325-12
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