Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

149 Pages·2015·5.09 MB·English

by  Prakash Harikumar

Linko¨ pingStudiesinScienceandTechnology
Dissertations,No.1728
Low-Voltage Analog-to-Digital Converters
and Mixed-Signal Interfaces
PrakashHarikumar
DivisionofIntegratedCircuitsandSystems
DepartmentofElectricalEngineering(ISY)
Linko¨ pingUniversity
SE-58183Linko¨ ping,Sweden
Linko¨ ping2015
Low-VoltageAnalog-to-DigitalConvertersandMixed-SignalInterfaces
Copyright©2015PrakashHarikumar
ISBN978-91-7685-890-5
ISSN0345-7524
PrintedbyLiU-Tryck,Linko¨ping,Sweden,2015
Abstract
Analog-to-digital converters (ADCs) are crucial blocks which form the interface
betweenthephysicalworldandthedigitaldomain. ADCsareindispensableinnumer-
ousapplicationssuchaswirelesssensornetworks(WSNs),wireless/wirelinecommu-
nicationreceiversanddataacquisitionsystems. Toachievelong-term,autonomous
operation for WSNs, the nodes are powered by harvesting energy from ambient
sources such as solar energy, vibrational energy etc. Since the signal frequencies
inthesedistributedWSNsareoftenlow,ultra-low-powerADCswithlowsampling
ratesarerequired. Theadventofnewwirelessstandardswithever-increasingdata
ratesandbandwidthnecessitatesADCscapableofmeetingthedemands. Wireless
standardssuchasGSM,GPRS,LTEandWLANrequireADCswithseveraltensof
MS/sspeedandmoderateresolution(8-10bits). SincetheseADCsareincorporated
into battery-powered portable devices such as cellphones and tablets, low power
consumptionfortheADCsisessential.
Thefirstcontributionisanultra-low-power8-bit,1kS/ssuccessiveapproximation
register(SAR)ADCthathasbeendesignedandfabricatedina65-nmCMOSprocess.
ThetargetapplicationfortheADCisanautonomously-poweredsoil-moisturesensor
node. At V = 0.4 V, the ADC consumes 717 pW and achieves an FoM =
DD
3.19fJ/conv-stepwhilemeetingthetargeteddynamicandstaticperformance. The
8-bitADCfeaturesaleakage-suppressedS/Hcircuitwithboostedcontrolvoltage
whichachieves>9-bitlinearity. Abinary-weightedcapacitivearraydigital-to-analog
converter (DAC) is employed with a very low, custom-designed unit capacitor of
1.9fF.ConsequentlytheareaoftheADCandpowerconsumptionarereduced. The
ADCachievesanENOBof7.81bitsatnear-Nyquistinputfrequency. Thecorearea
occupiedbytheADCisonly0.0126mm2.
The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and
implementedin65nmCMOSaimedatcommunicationapplications. Formedium-to-
highsamplingrates,theDACreferencesettlingposesaspeedbottleneckincharge-
redistributionSARADCsduetotheringingassociatedwiththeparasiticinductances.
Although SAR ADCs have been the subject of intense research in recent years,
scantattentionhasbeenlaidonthedesignofhigh-performanceon-chipreference
voltagebuffers. Theestimationofimportantdesignparametersofthebufferaswell
iv
criticalspecificationssuchaspower-supplysensitivity,outputnoise,offset,settling
timeandstabilityhavebeenelaborateduponinthisdissertation. Theimplemented
bufferconsistsofatwo-stageoperationaltransconductanceamplifier(OTA)combined
withreplicasource-follower(SF)stages. The10-bitSARADCutilizessplit-array
capacitiveDACstoreduceareaandpowerconsumption. Inpost-layoutsimulation
whichincludestheentirepadframeandassociatedparasitics,theADCachievesan
ENOBof9.25bitsatasupplyvoltageof1.2V,typicalprocesscornerandsampling
frequencyof50MS/sfornear-Nyquistinput. Excludingthereferencevoltagebuffer,
theADCconsumes697µWandachievesanenergyefficiencyof25fJ/conversion-step
whileoccupyingacoreareaof0.055mm2.
Thethirdcontributioncomprisesfivedisparateworksinvolvingthedesignofkey
peripheralblocksoftheADCsuchasreferencevoltagebufferandprogrammable
gainamplifier(PGA)aswellaslow-voltage,multi-stageOTAs. Theseworksarea)
Designofa1V,fullydifferentialOTAwhichsatisfiesthedemandingspecifications
ofaPGAfora9-bitSARADCin28nmUTBBFDSOICMOS.Whileconsuming
2.9 µW, the PGA meets the various performance specifications over all process
corners and a temperature range of [ 20 C +85 C]. b) Since FBB in the 28 nm
◦ ◦
−
FDSOIprocessallowswidetuningofthethresholdvoltageandsubstantialboostingof
thetransconductance,anultra-low-voltagefullydifferentialOTAwithV =0.4V
DD
hasbeendesignedtosatisfythecomprehensivespecificationsofageneral-purpose
OTAwhilelimitingthepowerconsumptionto785nW.c)Designandimplementation
ofapower-efficientreferencevoltagebufferin1.8V,180nmCMOSfora10-bit,
1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two
previously-published frequency compensation schemes on the basis of unity-gain
frequencyandphasemarginonathree-stageOTAdesignedina1.1V,40-nmCMOS
process.Simulationresultshighlightthebenefitsofsplit-lengthindirectcompensation
overthenestedMillercompensationscheme. e)Designofananalogfront-end(AFE)
satisfyingtherequirementsforacapacitivebody-coupledcommunicationreceiverin
a1.1V,40-nmCMOSprocess. TheAFEconsistsofacascadeofthreeamplifiers
followedbyaSchmitttriggeranddigitalbuffers. Eachamplifierutilizesatwo-stage
OTAwithsplit-lengthcompensation.
Popula¨rvetenskaplig
sammanfattning
Analog-till-digitalomvandlare(ADC)a¨rviktigabyggstenarfo¨rattkonverterasig-
naleridenfysiskava¨rldentilldendigitaladoma¨nen. AD-omvandlarea¨rno¨dva¨ndiga
i flera applikationer som tra˚dlo¨sa sensorna¨tverk (WSN), tra˚dlo¨s/tra˚dbundna kom-
munikationsmottagareochdatainsamlingssystem. Fo¨rattgetra˚dlo¨sasensornoder
la˚ngautonomlivsla¨ngdkandeutvinnaenergifra˚nsinomgivningexempelvisfra˚n
solenergi,ro¨relseenergietc. Eftersomfrekvensenpa˚insignalernaidessadistribuerade
sensornoderoftaa¨rla˚gbeho¨vsAD-omvandlaremedultrala˚geffektfo¨rbrukningochla˚g
samplingshastighet. A¨venskapandetavnyatra˚dlo¨sastandardermedsta¨ndigto¨kande
datatakter och bandbredd kra¨ver AD-omvandlare som kan tillgodose dessa krav.
Tra˚dlo¨sastandardersomGSM,GPRS,LTEochWLANbeho¨verAD-omvandlare
medsamplingshastigheterpa˚fleratiotalsmiljonersamplingarpersekundochmoderat
upplo¨sning(8-10bitar). EftersomAD-omvandlareanva¨ndsibatteridrivnaportabla
enhetersommobiltelefonerochsurfplattaa¨ra¨venla˚geffektfo¨rbrukningviktigt.
Detfo¨rstabidrageta¨ren8-bit,1kS/ssuccesivapproximationsregister(SAR)AD-
omvandlaremedultrala˚geffektfo¨rbrukningdesignadochtillverkadien65-nmCMOS
process. Applikationena¨renjordfuktighetssensornodsomsko¨rdarenergifra˚nsin
omgivning. Videnmatningsspa¨nningpa˚ 0.4Vfo¨rbrukarAD-omvandlaren717pW
ochharenFoMpa˚3,19fJ/konverteringsamtidigtsomdenmo¨terkravenpa˚dynamisk
ochstatiskprestanda. AD-omvandlarenharenla¨ckda¨mpandeS/Hkretsmedboost
kontrollsomna˚r>9bitarslinja¨ritet. Endigital-till-analogomvandlare(DAC)med
bina¨rviktadkapacitivarrayanva¨nds,arrayenanva¨nderenva¨ldigtlitenspecialgjord
enhetskapacitanspa˚ 1,9fFfo¨rattreduceraba˚deareanocheffektfo¨rbrukningenav
AD-omvandlaren. Denna˚renENOBpa˚7,81bitarfo¨rinfrekvenserna¨raNyquistfrek-
vensen. AD-omvandlarensareaa¨rbara0,0126mm2.
Detandrabidrageta¨ren1,2V,10-bit,50MS/sSARAD-omvandlaredesignad
ochimplementeradi65-nmCMOSfo¨rkommunikationsapplikationer. Fo¨rmedelho¨ga
tillho¨gasamplingshastigheterbegra¨nsarinsva¨ngningstidenfo¨rDA-omvandlarensref-
erensspa¨nninghastigheteniladdningsredistributionsSARAD-omvandlarepa˚ grund
avringningarorsakadavparasitiskainduktanser. TrotsattSARAD-omvandlarehar
vi
varitfokusfo¨rintensivforskningdesenastea˚renharintemycketforskninggjortspa˚
ho¨gpresterandeintegreradespa¨nningsreferensbuffrar. Estimeringavviktigadesign
parametrarfo¨rbuffernochkritiskaspecifikationersomka¨nslighetmota¨ndringarimat-
ningsspa¨nningen,utsignalsbrus,offset,insva¨ngningstidochstabilitetharunderso¨kts
idennaavhandling. Denimplementeradebuffernbesta˚raventva˚-stegsoperation-
stranskonduktansfo¨rsta¨rkare(OTA)kombineradmedettreplikerandesourcefo¨ljarsteg
(SF).AD-omvandlarenanva¨nderenkapacitivDA-omvandlaremeddeladarrayfo¨ratt
reduceraareanocheffektfo¨rbrukningen. Ipost-layoutsimuleringar,inklusiveallapin-
narochderasassocieradeparasiter,na˚rAD-omvandlaren9,25effektivabitar(ENOB)
med en matningsspa¨nning pa˚ 1,2 V, typiska processparametrar och en sampling-
shastighet pa˚ 50 MS/s fo¨r insignaler na¨ra Nyquist frekvensen. Utan spa¨nnings-
referensbuffernfo¨rbrukarAD-omvandlaren697µWochharenenergieffektivitetpa˚
25fJ/konverteringmedenareapa˚ 0,055mm2.
Det tredje bidraget besta˚r av fem olika arbeten besta˚ende av viktiga assister-
andeblockfo¨renAD-omvandlaresomspa¨nningsreferensbufferochprogrammerbara
fo¨rsta¨rkare(PGA)samtla˚gspa¨nnings,flerstegsOTAs. Dessaarbetena¨ra)Design
aven1V,differentiellOTAsommo¨terkravensomsta¨llsfo¨renPGAtillen9-bitars
SARAD-omvandlarei28-nmUTBBFDSOICMOS.Medeneffektfo¨rbrukningpa˚
2,9µWna˚rPGA:nallaspecifikationernao¨verallaprocessho¨rnochfo¨rtemperaturer
mellan 20 Ctill+85 C.b)EftersomFBBi28-nmFDSOItilla˚terstorajusteringar
◦ ◦
−
avtro¨skelspa¨nningenochboostningavtranskonduktansen,harendifferentiellOTA
medenmatningsspa¨nningpa˚ 0,4Vdesignatsfo¨rattmo¨taallakravsomsta¨llspa˚ en
universellOTAmedeneffektfo¨rbrukningpa˚ 785nW.c)Designochimplementation
aveneffekteffektivspa¨nningsreferensbuffermedenmatningsspa¨nningpa˚ 1,8Vi
180-nm CMOS fo¨r en 10-bitars, 1 MS/s SAR AD-omvandlare fo¨r en industriell
fingeravtrycksla¨sare. d)Ja¨mfo¨relseavtidigarepubliceradefrekvenskompensering-
steknikerfo¨rattmo¨takravenfo¨rfo¨rsta¨rkar-bandbredds-produktenochfasmarginalen
ientre-stegsOTAdesignadien1,1V,40-nmCMOSprocess. Simuleringsresultaten
visadepa˚fo¨rdelarnamedenindirektkompenseringja¨mfo¨rtmedMillerkompensering.
e) Design av ett analogt front-end (AFE) som tillgodoser kraven fo¨r en kapacitiv
kroppskoppladkommunikationsmottagareien1,1V,40-nmCMOSprocess. AFE:n
besta˚ravtreseriekoppladefo¨rsta¨rkarefo¨ljtavenSchmittriggerochendigitalbuffer.
Varjefo¨rsta¨rkareanva¨nderentva˚-stegsOTAmedindirektkompensering.
Preface
ThisdissertationpresentstheresearchworkperformedduringtheperiodAugust2011
September2015attheDepartmentofElectricalEngineering,Linko¨pingUniversity,
−
Sweden. Themaincontributionsofthisdissertationareasfollows:
• Design and implementation of a 0.4 V, 717 pW, 8-bit 1 kS/s SAR ADC in
65nmCMOS.TheADCfeaturesaleakage-reducedsamplingswitchwitha
multi-stagechargepumptoguaranteesufficientlinearity. Acustom-designed
unitcapacitorachievesreducedareaandpowerconsumptionforthecapacitive
DAC.
• Designandimplementationofa10-bit,50MS/sSARADCwithanon-chip
referencevoltagebufferin65nmCMOS.Thespeedlimitationformedium/high-
speedSARADCsduetoinaccurateDACsettlinginthepresenceofbondwire
parasiticsisdiscussed. Theperformancespecificationanddesigndetailsofa
high-speedreferencevoltagebufferareelaborateduponinthiswork.
• Designofalow-powerPGAfora9-bitSARADCin28nmUTBBFDSOI
CMOSprocess. TheRBBfeatureofthisCMOSprocessnodewasutilizedto
enhancetheDCgainwhileavoidinglargeresistorsintheCMFBcircuitforthe
firststage.
• Design of an ultra-low-voltage fully differential OTA in 28 nm UTBB FD-
SOICMOS.Withadifferentialoutputswingof0.8FS,theOTAachievesan
SNR of 8.7 bits and a THD of 60.3 dB while consuming 785 nW from a
−
0.4 V supply. The small-signal and large signal performance as well as the
matching-constrained specifications such as PSRR, CMRR and offset have
beendeterminedusingexhaustivesimulations.
• Design and implementation of a power-efficient reference voltage buffer in
180nmCMOSfora10-bit, 1MS/sSARADCinafingerprintsensor. The
buffermeetstherequirementsonsettlingtime,PSRR,outputnoise,stability
andalsosupportsalow-powerstandbymode.
viii
• Comparison of two previously-published frequency compensation schemes
using a three-stage OTA designed in 40 nm CMOS. Utilizing metrics such
as phase margin, unity-gain frequency and total compensation capacitance,
the advantages of the reversed nested indirect compensation technique are
illustratedforhigh-speedmulti-stageOTAs.
• DesignofareceiverAFEforcapacitivebody-coupledcommunicationin1.1V,
40nmCMOS.ThreedifferentAFEtopologiesweredesignedandcomparedin
termsofnoise,gainandpowerconsumption.
Thecontentsofthisdissertationarebasedonthefollowingpublications:
• PaperI P.Harikumar,J.J.WiknerandA.Alvandpour,“A0.4V,sub-nW,
−
8-bit1kS/sSARADCin65nmCMOSforWirelessSensorApplications”,
IEEETrans. CircuitsSyst. II(submitted).
• PaperII P.HarikumarandJ.J.Wikner,“A10-bit50MS/sSARADCin
−
65nmCMOSwithon-chipreferencevoltagebuffer”,ElsevierIntegration,the
VLSIJournal,vol.50,pp. 28-38,June2015.
• PaperIII P.HarikumarandJ.J.Wikner,“DesignofaSamplingSwitch
−
for a 0.4 V SAR ADC Using a Multi-Stage Charge Pump”, in Proc. IEEE
NorchipConf.,Tampere,Finland,pp. 1-4,Oct. 2014.
• PaperIV P.HarikumarandJ.J.Wikner,“DesignofaReferenceVoltage
−
Bufferfora10bit,50MS/sSARADCin65nmCMOS”,inProc. IEEEInt.
Symp. CircuitsSyst. (ISCAS),Lisbon,Portugal,pp. 249-252,May2015.
• PaperV P.Harikumar,J.J.Wikner,andA.Alvandpour,“AFully-Differential
−
OTAin28nmUTBBFDSOICMOSforPGAApplications”,inProc.European
Conf. CircuitTheoryandDesign(ECCTD),Trondheim,Norway,pp. 1-4,Aug.
2015.
• PaperVI P.Harikumar,J.J.Wikner,andA.Alvandpour,“AnUltra-Low-
−
VoltageOTAin28nmUTBBFDSOICMOSUsingForwardBodyBias”,in
Proc. IEEENordicCircuitsandSystemsConf. (NORCAS),Oslo,Norway,pp.
1-4,Oct. 2015.
• Paper VII P. Harikumar, P. Angelov, and R. Ha¨gglund, “Design of a
−
ReferenceVoltageBufferfora10-bit1-MS/sSARADC”,inProc. Int. Mixed
DesignofIntegratedCircuitsandSystems(MIXDES)Conf.,Lublin,Poland,
pp. 185-188,June2014.
• Paper VIII S. A. Aamir, P. Harikumar and J. J. Wikner, “Frequency
−
CompensationofHigh-Speed,Low-VoltageCMOSMultistageAmplifiers”,in
ix
Proc. IEEEInt. Symp. CircuitsSyst. (ISCAS),Beijing,China,pp. 381-384,
May2013.
Contribution: Idesignedathree-stageOTAin40nmCMOSandemployed
twofrequencycompensationschemesonit. Icarriedouttherelevantsimula-
tionsandplayedamajorroleinmanuscriptpreparation. Aamirdesignedand
simulatedthefour-stageOTAin65nmCMOSandwasinvolvedinmanuscript
preparation.
• PaperIX P.Harikumar,M.I.Kazim,andJ.J.Wikner,“Ananalogreceiver
−
front-endforcapacitivebody-coupledcommunication”,inProc. IEEENorchip
Conf.,Copenhagen,Denmark,pp. 1-4,Nov. 2012.
Contribution: Idesignedatwo-stageOTAin40nmCMOSaswellasthethree
AFEtopologies. Icarriedoutthenecessarysimulationsandplayedamajor
roleinmanuscriptpreparation. Thecalculationofthenoiselevelallowedfor
theAFEwasprovidedbyJacob. Irfanwasresponsibleforincludingthedetails
ofthehumanbodyelectricalmodelanddiscretetransceiverrealization.
Thefollowingpaperswerealsopublishedduringthisperiodwhichareoutside
thescopeofthisdissertation:
• K.Chen,P.HarikumarandA.Alvandpour,“Designofa12.8ENOB,1kS/s
PipelinedSARADCin0.35-µmCMOS”,AnalogIntegr. Circ. Sig. Process.,
2015(Accepted).
• M.Nielsen-Lo¨nn,P.Harikumar,J.J.Wikner,andA.Alvandpour,“Design
ofEfficientCMOSRectifiersforIntegratedPiezo-MEMSEnergy-Harvesting
PowerManagementSystems”,inProc. EuropeanConf. CircuitTheoryand
Design(ECCTD),Trondheim,Norway,pp. 1-4,Aug. 2015.
x