Low-Voltage Analog CMOS Architectures and Design Methods

161 Pages·2016·5.83 MB·English

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Theses and Dissertations
2007-11-16
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Kent Downing Layton
Brigham Young University - Provo
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Layton, Kent Downing, "Low-Voltage Analog CMOS Architectures and Design Methods" (2007). Theses
and Dissertations. 1218.
https://scholarsarchive.byu.edu/etd/1218
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LOW-VOLTAGE ANALOG CMOS ARCHITECTURES
AND DESIGN METHODS
by
Kent D. Layton
A dissertation submitted to the faculty of
Brigham Young University
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
Department of Electrical and Computer Engineering
Brigham Young University
December 2007

Copyright (cid:176)c 2007 Kent D. Layton
All Rights Reserved

BRIGHAM YOUNG UNIVERSITY
GRADUATE COMMITTEE APPROVAL
of a dissertation submitted by
Kent D. Layton
This dissertation has been read by each member of the following graduate committee
and by majority vote has been found to be satisfactory.
Date Donald T. Comer, Chair
Date David J. Comer
Date Richard H. Selfridge
Date Michael A. Jensen
Date Doran K. Wilde

BRIGHAM YOUNG UNIVERSITY
As chair of the candidate’s graduate committee, I have read the dissertation of Kent
D. Layton in its final form and have found that (1) its format, citations, and bibli-
ographical style are consistent and acceptable and fulfill university and department
style requirements; (2) its illustrative materials including figures, tables, and charts
are in place; and (3) the final manuscript is satisfactory to the graduate committee
and is ready for submission to the university library.
Date Donald T. Comer
Chair, Graduate Committee
Accepted for the Department
Michael J. Wirthlin
Graduate Coordinator
Accepted for the College
Alan R. Parkinson
Dean, Ira A. Fulton College of
Engineering and Technology

ABSTRACT
LOW-VOLTAGE ANALOG CMOS ARCHITECTURES
AND DESIGN METHODS
Kent D. Layton
Department of Electrical and Computer Engineering
Doctor of Philosophy
This dissertation develops design methods and architectures which allow ana-
log circuits to operate at V +2V , the minimum supply for CMOS circuits with
T ds,sat
all transistors in the active region where V is the drain to source saturation volt-
ds,sat
age of a MOS transistor. Techniques which meet this criteria for rail-to-rail input
stages, gain enhancement stages, and output stages are discussed and developed.
These techniques are used to design four fully-differential rail-to-rail amplifiers. The
highest gain is shown to be attained using a drain voltage equalization (DVE) or
active-bootstrapping technique which produces more than 100dB of gain in a two
stage amplifier with a bulk-driven input pair while showing no bandwidth degrada-
tion when compared to amplifier architectures with similar biasing. The low voltage
design techniques are extended to switching and sampling circuits. A 10-bit digi-
tal to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are
designed and fabricated in a 0.35µm dual-well CMOS process to prove the devel-
oped design methods, architectures, and techniques. The 10-bit DAC operates at