Logic Design for Array-Based Circuits: A Structured Design Methodology

271 Pages·1992·8.91 MB·English

by  D. E. White

Logic Design for Array-Based Circuits

by Donnamaie E. White
Copyright © 1996, 2001, 2002 Donnamaie E. White

The original form of this book was published by Academic Press, 1250 Sixth
Avenue, San Diego, California 92101-4311 in 1992. ISBN 0-12-746660-6.
The figures were reproduced with the permission of Applied Micro Circuit
Corporation. The Q20000 Series and other bopolar and BiCMOS series
referenced belong to AMCC. Note that this book is dated as to the AMCC
ASIC business. It represents design flow from the late 1980's to early
1990's. Thge design flow bears a remarkable similarity to the current design
flow used by Cadence and Synopsis - with the switch from schematic
capture to HDL code and synthesis and with more of the validation steps
now performed by various software programs. A basic understanding of the
underlying methodology to what we do today with deep submicron
technologies is still a good read. Everything that bipolar design had to
handle in the early 1980's is what we now must handle for 0.25 micron and
belowCMOS technologies.
This book was based on classes taught at USCD and at AMCC's customer
Design Center.

Customer training courses prepared by high-technology vendors are a
required extension to that training available in the engineering classes at
the college level. The quality of that training can vary with the experience of
the instructor. The experience of the instructor with the nuances of the
products is one facet. The teaching expertise is another. The purpose behind
this book was to document what a proven instructor was adding to the
course material and manuals. By providing this supplement, it would be
possible for other, less experienced instructors, to take over the actual
presentation of the seminars while ensuring no loss of insight into the
methodology or product taught.
l Table of Contents
l Preface
l Overview
m Introduction
m Integration Levels
m Demand and Supply
m eLearning - the Next Best Thing
l Chapter 1 Introduction
m Introduction
m Selection
m Design Support Issues
n Schematic Rules Checking
n Reformatters
n Design Upgrades
m Exercises
m Update 2000
l Chapter 2 Structured Design Methodology
m Structured Design Methodology
m Review of the Available Arrays
m Initial Sizing of the Circuit
m Create the Preliminary Macro Schematic (when schematics are
used)
m Compute the Path Propagation Delay
m Compute the Estimated Power
m Pre-Simultation Steps
m Simulation
m Fault Grading
m Design Submission Through Prototype
n Design Validation Review
n Placement
l Chapter 3 Sizing the Design
m Functional Specification - A Closer Look
m Review the Available Arrays
m Architectual Specification or Hardware Specification
m Array Sizing
m Cell Capabilities
m Array Architecture
m Netlist
m Example - AMCC Arrays - Power Supply Options
m Examples
m Refining Interface Requirements
m Dual-Function I/O Macros
m Thermal Diodes
m Final Interface Cell Utilization
m Drivers
m Exercises
l Chapter 3 Appendix = Case Study in Sizing a Design
l Chapter 4 Design Optimization
m Introduction
m Optimization Approaches
m Design to Improve Speed
m Example of Silicon Efficiency
m Internal Net Delays
m Design to Reduce Internal Cell Utilization
m Design to Reduce I/O Utilization
m Design to Fit the Package
m Design to Reduce Power
m Design to Reduce Cost
m Basic Design for Circuit Testability
m Basic Design for Circuit Reliability
m Design to Reduce Cost
m Exercises
l Chapter 5 Timing Analysis for Arrays
m Introduction
m Path Propagation Delay Overview
m Intrinsic Set-Up and Hold Time
m Interconnect Delays
m Annotation
m Manual Computation - One Method
m Example Equations for Extrinsic Loading - Internal Nets
m k-Factors
m Computing Lfo
m Computing Lwo
m Computing Lnet
m Example Equations for Extrinsic Loading - Output Nets
m Worst-Case Delay Multiplication Factors
m Front Annotation
m Intermediate Annotation
m Back Annotation
m Exercises
l Chapter 6 External Set-up and Hold Times
m Introduction
m Case 1: When the Timing Specifications Are Nominal
m Case 2: When The Timing Specifications Are Worst-Case
m Example - AMCC Q1400 BiCMOS Series
m Example - AMCC Q20000 Bipolar Series
m Case Study: Preventing Hold Violations Due To Clock Skew
m Computing Hold Time in the Register Example
l Chapter 7 Power Considerations
m Introduction
m DC Power---
m AC Power
m Worst-Case Power
m Power Reduction Techniques
m Design Rules for Power Reduction (AMCC)
m Computing DC Power Dissipation
m AC Macro Power Dissipation
l Case Study: DC Power Computation
m Step 10: Determine ECL Static Power PEO
l Case Study: AC Power Computation
m Total Power Dissipation
l Chapter 8 Simulation
m Introduction
m Simulators - The Tools
m Wafer Sort/Packages Part Sort Functional Simulation
m At-Speed Simulation For Timing Verification
m AC Tests
m Parametric Vectors
m Hazards
l Case Study: Simulation
m Functional Simulation
m Parametric Simulation
m At-Speed Simulation
m AC Test
l Chapter 9 Faults and Fault Detection
m Introduction
m Fault Types
m The Problem
m Selecting a Chain
m Case Study - 16:1 MUX
m 2:1 MUX Example
m 3:1 MUX
m Actual Test Vector Sequence for a 16:1 MUX with Clocked
Output
l Chapter 10 Design Submission
m Case Study: AMCC Design Submission
m Continued
m Functional Simulation Submission (Required)
m At-Speed Simulation Submission (Required)
m AC Tests Path Delay Vector Submission (Optional)
m Parametric Vectors (Required or Optional)
l ASIC Glossary
m Glossary A-D
m Glossary E-K
m Glossary L-R
m Glossary S-Z
m
Preface

This book was based on classes taught at USCD and at AMCC's
customer Design Center 1984 - 1994. It is based on schematic capture
rather than Verilog or VHDL input and on manual support rather than the
newer tools available for static timing verification, test generation,
synthesis, etc. The Design Flow is, however, still the same. The steps must
be done, with or without tools. This book details the theory behind the new
EDA tools.

Customer training courses prepared by high-technology vendors are a
required extension to that training available in the engineering classes at
the college level. The quality of that training can vary with the experience
of the instructor. The experience of the instructor with the nuances of the
products is one facet. The teaching expertise is another. The purpose
behind this book was to document what a proven instructor was adding to
the course material and manuals. By providing this supplement, it would be
possible for other, less experienced instructors, to take over the actual
presentation of the seminars while ensuring no loss of insight into the
methodology or product taught.
The course on which the book was based was rewritten for each new array
series and technology change made by Applied Micro Circuits Corporation.
The array series covered originally included the bipolar Q700 (1000 gates
on a chip running at 200 MHz) and ends with the Q20000 (20000 gates on
a chip running at 1.2 GHz), with CMOS and BiCMOS added along the way.
Structured Design
In the process of these rewrites, it became obvious that a certain core of
the seminar remained inviolate - the structured, orderly, logical
approach to circuit design . This approach was taken from discrete
board design, from SSI-MSI logic design, from bit-slice design, from
structured software and firmware programming, and from systems
concepts. This core material is represented in this text. The emphasis is on
the total design picture - all those myriad of details that interleave.
What was also obvious is that examples that are wrong as well as those
that are right are essential to rapid assimilation of the material. The last
array series turned to for examples was the 1994-1995 AMCC Q20000
Bipolar array series.
The goal has been to create a book that can be used with any vendor's
array series. It applies those designing circuits for an ASIC, Application
Specific Integrated Circuit, vendor to produce, and to those vendors who
are designing ASSPs, Application Specific Special Products, standard
products that are designed to be built on an array base wafer. (ASSPs are
the latest addition to the designer's toolbox.)
Acknowledgments
The author would like to thank the AMCC staff for their time and energy
expended in the compilation of this material, with specific thanks to
Richard W. Spehn for his expertise and encouragement.
Overview
Last Edit July 22, 2001
Introduction
Each of the last six decades has seen a new technology come forward as the
leading edge for that era. Table 1 provides a summary of this evolution by
decade and integration level.
Table 1 - Integrated Circuit Evolution
Approx. Date Size Description
A few transistors and other
1950s gate level components combined to form an
AND, OR or NOR gates
4 or more gates; NAND, NOR, OR,
mid 1960s SSI
AND, EXOR, NOT or INVERT
up to 200 gates; registers,
early 1970s MSI
decoders, multiplexors, etc.
several hundred gates; ALUs with
scratch-pad registers, interrupt
late 1970s LSI
controllers, microprogram
sequencers, ROMs, PROMs
700 gates and up; CPUs, complex
1980s VLSI
functions
up to 30,000 gates; multiple
1980s ASIC
functions
up to 100,000 gates and increasing
early 1990s ASIC
with speeds at 1.4GHz and higher
The development of analog circuit
1980-1990s EPAC
arrays
Deep SubMicron (< 0.18µ) designs;
DSM 1 Million gate arrays; System on a
1990s SoC Chip
IP Intellectual Property - soft and hard
IP building blocks
Deep SubMicron (0.13µ) designs; 4-
Design Reuse 10 Million gate arrays; more gates,
2000 and up (IP); faster designs; improved test
High-speed methodology; faster synthesis
the 1 GHz and faster CPUs
Each technology change has led to a period where those designers who are
state-of-the-art orientated, those who readily delve into new developments,
accept and begin to use the newest devices in designs.
For successful technologies, this is followed by the intense application and
development phase where the high demand for engineers who can design
with the devices typically exceeds the supply of those engineers. The is the
driving force behind the evolution of IP (Intellectual Property) blocks,
predesigned mega-function blocks that can be re-used in more than one
chip.
These mega-functions become part of the design library.They may be hard-
IP, where all levels of the base die are involved, or soft-IP, where only the
metallization layers (currently about 6-8 layers of the die) are involved.
Integration Levels
From the mid-1960s, there are small-scale integration (SSI) gates: NAND,
NOR, EXOR, and NOT or INVERT. SSI can be defined to be about 2-10 gates
on a single chip. Anything can be built from SSI, but the design time,
power, and size make this approach obsolete for designs that must be built
quickly and in quantity. Custom design at the transistor and resistor level is
reserved for special projects.
From the early 1970s there are larger blocks, medium-scale integration
(MSI): registers, decoders, multiplexors, counters, adders, comparators,
etc. MSI is loosely defined as approximately 20-100 gates. MSI allows more
modular designs, speeding the design process when the blocks could be
applied.
In the late 1970s arithmetic logic units (ALUs) with on-board registers,
microprogrammable sequencers and interrupt controllers in a bit-slice
format became available. Memory chips (ROM, PROM, RAM) in increasing
sizes became readily available. Large-scale integration (LSI) culminated in
the one-chip microprocessors.
LSI is loosely defined as approximately 200-1000+ gates. Very large scale
integration (VLSI) has reached 20,000 gates and higher. LSI and VLSI
further increase the modular block size, reducing design time, space, and
power considerations and increasing reliability as connections are moved
inside the components. Many LSI and VLSI blocks are designed by their
manufacturers and referred to as fixed-instruction-set modules.
Bit-Slice Design
For any given design, if the architecture of the fixed LSI and VLSI blocks
suit the application then the design time is considerably shortened. When a
one-chip microprocessor is not quite suitable, microprogrammable
architectures can often provide sufficient customization.
Microprogrammable architectures, such as bit-slice, allow a closer control
over the architecture but not total control. The basic building blocks are still
designed by the chip manufacturer for generic applications. Bit-slice
architectures include interruptable sequencers and 32-bit ALUs.
The customization of the bit-slice modules to an application is done through
customer-designed module interconnection, the implemented commands
and their sequences. The commands or instruction set is called the micro-
program for the design.
ASIC
The 1980s saw the acceptance of ASICs ( application specific integrated
circuits), VLSI devices large enough to allow designers to implement
architectures that were suited to solving the design problem rather than
forcing one architecture to solve everything. It was the natural extension to
the bit-slice architectures, where some control of architecture was possible
through microprogramming but where the basic building blocks were fixed
designs. The application-specific customization of the design solution allows
the designer to have the creative power of a gate-level breadboard design
while keeping the production advantages of VLSI.
Not far behind the ASIC and ASIC developments, multimedia and design
integration saw a need to incorporate analog functions into digital systems.
For years the trend had been away from analog design as a chosen career
and now there was a shortage of design engineers. First came massive re-
training of internal staff as companies struggled to cope. Then came the
creation of Electrically Programmable Analog Circuit (EPAC) and related
devices.
Now designers are coping with 8-12 inch wafers, 1 million gate chips, a
deep submicron technologies with a shrinking design time window. For
example, the next-generation Pentium chips are mandated to be first-time
silicon success. The first took four tapeouts to achieve success.
Table 2 Integration Sizing Terminology
Acronym Definition
small scale integration where a few gates were lumped
SSI together as a means of improving the design and the design
process,
medium scale integration when more gates were packed
MSI
together in a single chip for the same reasons,
large scale integration when functional blocks could be
LSI
contained on a chip,
very large scale integration and its various offshoots (VHLSI,
VLSI etc.) where larger functional blocks and their related circuitry
could be brought together in lower power, faster chips.
ASIC application-specific integrated circuit
ASSP application specific standard product
EPACtm Electrically Programmable Analog Circuit
ALU arithmetic-logic unit
CPU central processor unit
DSM Deep SubMicron
VDSM Very Deep SubMicron
SoC System-on-a-chip
Intellectual Property - precoded functional block for design re-
IP
use (Hard-IP, Soft-IP)

Business
Systems
Demand And Supply
The number of designers who can successfully complete the design of an
array-based circuit through design submission and prototype acceptance is
limited. Some estimates as of 1998 are as low as 50,000 engineers in the
USA. The demand for array-based circuit designers is already predicted by
the periodicals to exceed the supply of trained engineers.
The demand for designers capable of fast, efficient and successful design
with ASICs is exceeding the supply and the predictions for the future show a
projected shortage. In addition to adding engineers to meet the demand,
the productivity of each designer will need to be drastically increased.
Designers must choose from a complex array of new products, new
technologies, changing standards, a wide range of support, changes in
packaging, varied design tools, and changing design rules, while evaluating
cost-effectiveness of the final product. Workstations are evolving, changing
platforms, expanding features, and moving from device to board to system
level capabilites.
Note: While this book was being written, Daisy went from one of the leading
vendors to nothing, Valid transferred to the SUN platform, obsoleting the
SCALD system, hardware emulators were beginning to be interesting, virtual
memory was recognized as probably useful for the big designs, the average
array speed went from 280MHz to over 1.2Ghz, the ASIC array size went
from 1000 gates to over 100,000 gates (30,000 useable), and design rules
for the newer arrays were rated as four times more complicated then
before. In the time since, we have reached successful 750,000 gate designs
and higher, have reduced technology from 0.35 to 0.18 micron and
switched from schematic capture to Verilog or VHDL input. Design tools
have advanced to pick up the intermediate steps between the larger
packages and tools to remove manual operations and make on-screen
design a reality. Array vendors start as many FPGAs and ASICs and are
outsourcing their libraries. EDA houses are supplying libraries alsog with a
full design flow tools set, usually with the intention of being the sole vendor
for all of the array designer's needs.
With the size, simulations became longer and 4K vectors were no longer a
reasonable limit for test vectors, packaging was pushed to its limits and
beyond, simulators were faced with the need for hardware-assist, timing
verifiers became non-unique in the design cycle, frameworks began to be
spoken of if not heavily used, behavioral languages (HDL, VHDL) were
accepted in marketing vocabulary and then supported - and are now the
accepted design start. These changes are only some of the ongoing
evolution made over the past five years.
Pick up any magazine or newspaper devoted to ASIC and at least one article
will decry the monumental task facing the design engineer in the 90's and
forward. There is a constant need to acquire new skills, understand and
master new tools and accept new array design restrictions and features.
And not only is the designer faced with the choice of which vendor and what
product, but also with the management of the design once started. The
design tools that do exist may not work together making design
management a complex and error-prone process.
As with any new technology, the engineer can choose to study the product
and its support from the design manuals, datasheets and reading literature.
ASIC array vendors provide design manuals to assist the designer in
completing a successful design submission, that point of transfer between
the design and the vendor.
Vendors maintain applications support engineers to answer questions and to
guide the customer-designer through the submission process. This "earn
while you learn" is acceptable in some cases, where design schedules will
allow the weeks or months it takes for the engineer to "get up to speed" and
to redo those design phases that failed due to misunderstanding of the
technology and its limits.
eLearning - Next Best Thing
When I first composed this text, back in the early 1990s, little did I realize
how much the industry would leap forward. None of us were prepared for

the advance of the Internet, although e-mail had been with the engineering
community since the 1960s and FTP had been in use since at least that
time. HTML burst upon the scene and several of us clicked on the concept of
"living" classrooms on the web almost instantly. In 2001, Harvard put its
entire curriculum on-line (for free). Cadence has put all of its technical
training classes on-line (for a fee). Synopsys has begun to put its technical
training on the web.
The industry has spawned expensive-to-produce CD ROM training, which
has not been widely accepted, page-turners (PowerPoint presentations
with/without audio and with/without video assist, "live" webcasts or update
training, and fully-integrated, true computer-based instruction.
The goal is to have "living" technical material that can be updated faster
than the two-year cycle for a technical book or the six-month cycle of a
technical journal. The web is immediate.
This author has just completed the conversion of the Synopsys Advanced
Chip Synthesis 3-day lecture-lab Workshop into the Advanced Chip
Synthesis eLearning Workshop, hosted at Vitalect. This is the first of several
planned course conversions. The workshops will still be available in ILT form
(Instructor Led Training) as well.
There is a free on-line Advanced Chip Synthesis Demo featuring one of the
workshop Units. You can view the demo at Vitalect but your browser must
be configured with RealAudio and Flash for proper display of animations and
to hear the audio scripts. Vitalect features a "Set-Up" page to help you.
Training Classes - Historical Review
ASIC, library and EDA vendors offer training classes where the array
product and its peripheral requirements for design submission are presented
in intense two to five day seminars and workshops. Because of the structure
of a class, the array vendor can attempt to ensure that important issues are
discussed or at least brought to the attention of the designers. This reduces
the problems that could occur during the acceptance review of the design
submission which shortens the first-time design cycle.
AMCC - Applied Micro Circuits Corporation - offered a three-day array design
class and a two-day workshop workstation lab class to its customers. This
class was taught for seven years, using the same methodology for a range
of evolving products: Bipolar Q700 Series, Q1500, QH1500, Q3500 Series,
Q5000 Series, Q20000 Series; CMOS Q6000 Series, Q6000A Series, Q9000
Series; BiCMOS Q14000 Series; and Q24000 Series.